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公开(公告)号：US20170223841A1
公开(公告)日：2017-08-03
申请号：US15488519
申请日：2017-04-17
Applicant: Unimicron Technology Corp.
Inventor： Chun-Ting Lin
IPC: H05K3/40 , H01L21/677 , H01L21/67 , H01L21/673 , H05K1/11
Abstract: A carrier substrate includes a circuit structure layer, a first solder resist layer, a second solder resist layer and conductive towers. The circuit structure layer includes a core structure layer, a first circuit layer and a second circuit layer. The first solder resist layer has first openings exposing a portion of the first circuit layer. The second solder resist layer has second openings exposing a portion of the second circuit layer. The conductive towers are disposed at the first openings, higher than a surface of the first solder resist layer and connected with the first openings exposed by the first circuit layer, wherein a diameter of each of the conductive towers gradually increases by a direction from away-from the first openings towards close-to the first openings. A diameter of the second conductive towers is greater than that of the first conductive towers.
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公开(公告)号：US09491871B2
公开(公告)日：2016-11-08
申请号：US14977669
申请日：2015-12-22
Applicant: Unimicron Technology Corp.
Inventor： Ying-Chih Chan , Chun-Ting Lin
CPC classification number: H05K3/4015 , H05K3/0097 , H05K3/4644 , H05K2201/09509 , H05K2201/09827 , H05K2203/041 , H05K2203/1536
Abstract: A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings exposing the first circuit layer. The conductive blocks fill the first openings and connect with the first circuit layer. A top surface of each of the conductive blocks is higher than the third surface of the insulation layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.
Abstract translation: 载体基板包括电介质层，第一电路层，绝缘层，导电块和第一导电结构。 电介质层具有第一表面，第二表面和盲孔。 第一电路层嵌入在第一表面中，盲孔从第二表面延伸到第一电路层。 绝缘层设置在第一表面上，并且具有第三表面，第四表面和暴露第一电路层的第一开口。 导电块填充第一开口并与第一电路层连接。 每个导电块的顶表面高于绝缘层的第三表面。 第一导电结构包括填充盲通孔的导电通孔和设置在第二表面的一部分上的第二电路层。
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公开(公告)号：US09247654B2
公开(公告)日：2016-01-26
申请号：US13966295
申请日：2013-08-14
Applicant: Unimicron Technology Corp.
Inventor： Chun-Ting Lin
CPC classification number: H05K3/4015 , H05K3/0097 , H05K3/4644 , H05K2201/09827 , H05K2203/041 , H05K2203/1536
Abstract: A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings. The first openings expose the first circuit layer and an aperture of each first opening is increased gradually from the third surface to the fourth surface. The conductive blocks fill the first openings and connect with the first circuit layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.
Abstract translation: 载体基板包括电介质层，第一电路层，绝缘层，导电块和第一导电结构。 电介质层具有第一表面，第二表面和盲孔。 第一电路层嵌入在第一表面中，盲孔从第二表面延伸到第一电路层。 绝缘层设置在第一表面上并且具有第三表面，第四表面和第一开口。 第一开口露出第一电路层，并且每个第一开口的开口从第三表面逐渐增加到第四表面。 导电块填充第一开口并与第一电路层连接。 第一导电结构包括填充盲通孔的导电通孔和设置在第二表面的一部分上的第二电路层。
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公开(公告)号：US09408313B2
公开(公告)日：2016-08-02
申请号：US14174858
申请日：2014-02-07
Applicant: Unimicron Technology Corp.
Inventor： Chun-Ting Lin , Ying-Chih Chan
CPC classification number: H05K3/4007 , H01L2224/13017 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/81385 , H05K3/062 , H05K2201/0367 , H05K2201/0376 , Y10T29/49156 , H01L2924/014 , H01L2924/00014
Abstract: A packaging substrate is provided, including a substrate body and conductive pillars. The substrate body has a first surface and a second surface opposite to the first surface. The first surface has a plurality of first conductive pads, and the second surface has a die attach area and a peripheral area surrounding the die attach area. The die attach area has a plurality of second conductive pads embedded therein, wherein top surfaces of the second conductive pads are exposed from the second surface, and the die attach area of the second surface is fully exposed. The conductive pillars are correspondingly disposed on the second conductive pads and have first ends and opposite second ends. The first ends are closer than the second ends from the second conductive pads, and the first ends have a width bigger than a width of the second ends. A fabricating method thereof is also provided.
Abstract translation: 提供了一种包装基板，包括基体和导电支柱。 基板主体具有与第一表面相对的第一表面和第二表面。 第一表面具有多个第一导电焊盘，第二表面具有管芯附着区域和围绕管芯附着区域的周边区域。 管芯附着区域具有嵌入其中的多个第二导电焊盘，其中第二导电焊盘的顶表面从第二表面露出，并且第二表面的管芯附着区域被完全暴露。 导电柱相应地设置在第二导电焊盘上并且具有第一端和相对的第二端。 第一端比第二导电焊盘更靠近第二端，并且第一端的宽度大于第二端的宽度。 还提供了其制造方法。
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公开(公告)号：US20160113114A1
公开(公告)日：2016-04-21
申请号：US14977669
申请日：2015-12-22
Applicant: Unimicron Technology Corp.
Inventor： Ying-Chih Chan , Chun-Ting Lin
CPC classification number: H05K3/4015 , H05K3/0097 , H05K3/4644 , H05K2201/09509 , H05K2201/09827 , H05K2203/041 , H05K2203/1536
Abstract: A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings exposing the first circuit layer. The conductive blocks fill the first openings and connect with the first circuit layer. A top surface of each of the conductive blocks is higher than the third surface of the insulation layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.
Abstract translation: 载体基板包括电介质层，第一电路层，绝缘层，导电块和第一导电结构。 电介质层具有第一表面，第二表面和盲孔。 第一电路层嵌入在第一表面中，盲孔从第二表面延伸到第一电路层。 绝缘层设置在第一表面上，并且具有第三表面，第四表面和暴露第一电路层的第一开口。 导电块填充第一开口并与第一电路层连接。 每个导电块的顶表面高于绝缘层的第三表面。 第一导电结构包括填充盲通孔的导电通孔和设置在第二表面的一部分上的第二电路层。
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Patent Agency Ranking
公开(公告)号：US20140332253A1
公开(公告)日：2014-11-13
申请号：US13966295
申请日：2013-08-14
Applicant: Unimicron Technology Corp.
Inventor： Chun-Ting Lin
CPC classification number: H05K3/4015 , H05K3/0097 , H05K3/4644 , H05K2201/09827 , H05K2203/041 , H05K2203/1536
Abstract: A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings. The first openings expose the first circuit layer and an aperture of each first opening is increased gradually from the third surface to the fourth surface. The conductive blocks fill the first openings and connect with the first circuit layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.
Abstract translation: 载体基板包括电介质层，第一电路层，绝缘层，导电块和第一导电结构。 电介质层具有第一表面，第二表面和盲孔。 第一电路层嵌入在第一表面中，盲孔从第二表面延伸到第一电路层。 绝缘层设置在第一表面上并且具有第三表面，第四表面和第一开口。 第一开口露出第一电路层，并且每个第一开口的开口从第三表面逐渐增加到第四表面。 导电块填充第一开口并与第一电路层连接。 第一导电结构包括填充盲通孔的导电通孔和设置在第二表面的一部分上的第二电路层。
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公开(公告)号：US10820426B2
公开(公告)日：2020-10-27
申请号：US15488519
申请日：2017-04-17
Applicant: Unimicron Technology Corp.
Inventor： Chun-Ting Lin
IPC: H05K3/40 , H05K3/46 , H01L21/67 , H01L21/673 , H01L21/677 , H05K1/11 , H05K3/06 , H01L23/00
Abstract: A carrier substrate includes a circuit structure layer, a first solder resist layer, a second solder resist layer and conductive towers. The circuit structure layer includes a core structure layer, a first circuit layer and a second circuit layer. The first solder resist layer has first openings exposing a portion of the first circuit layer. The second solder resist layer has second openings exposing a portion of the second circuit layer. The conductive towers are disposed at the first openings, higher than a surface of the first solder resist layer and connected with the first openings exposed by the first circuit layer, wherein a diameter of each of the conductive towers gradually increases by a direction from away-from the first openings towards close-to the first openings. A diameter of the second conductive towers is greater than that of the first conductive towers.
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公开(公告)号：US20180027652A1
公开(公告)日：2018-01-25
申请号：US15263388
申请日：2016-09-13
Applicant: Unimicron Technology Corp.
Inventor： Chun-Ting Lin , Tsung-Si Wang
CPC classification number: H05K1/0296 , H05K1/09 , H05K1/115 , H05K3/007 , H05K3/064 , H05K3/181 , H05K3/188
Abstract: A circuit board including a substrate, a patterned circuit layer and a photo-imaginable dielectric layer is provided. The substrate has a first surface and a second surface opposite to each other. The patterned circuit layer is disposed on the first surface, and a line width of the patterned circuit layer gradually reduces from the first surface towards the second surface. The photo-imaginable dielectric layer is disposed in the substrate corresponding to the patterned circuit layer. In addition, a manufacturing method of the circuit board is also proposed.
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公开(公告)号：US09661761B2
公开(公告)日：2017-05-23
申请号：US13965194
申请日：2013-08-13
Applicant: Unimicron Technology Corp.
Inventor： Chun-Ting Lin
CPC classification number: H05K3/40 , H01L21/67265 , H01L21/673 , H01L21/67346 , H01L21/67763 , H01L21/6779 , H01L24/16 , H01L2224/16225 , H01L2924/0132 , H01L2924/0133 , H01L2924/12042 , H05K1/11 , H05K3/06 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/0979 , H05K2203/0369 , H05K2203/0376 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/00
Abstract: A carrier substrate includes an insulation layer, conductive towers and a circuit structure layer. A diameter of each of the conductive towers is increased gradually from a top surface to a bottom surface, and the conductive towers include first conductive towers and second conductive towers surrounding the first conductive towers. The circuit structure layer is disposed on the insulation layer and includes at least one dielectric layer, at least two circuit layers and first conductive vias. Each of the second conductive towers correspondingly connects to at least two of the first conductive vias, and each of the first conductive towers correspondingly connects to one of the first conductive vias. An interface exists between the first conductive vias and the first and the second conductive towers.
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公开(公告)号：US20140332252A1
公开(公告)日：2014-11-13
申请号：US13965194
申请日：2013-08-13
Applicant: Unimicron Technology Corp.
Inventor： Chun-Ting Lin
CPC classification number: H05K3/40 , H01L21/67265 , H01L21/673 , H01L21/67346 , H01L21/67763 , H01L21/6779 , H01L24/16 , H01L2224/16225 , H01L2924/0132 , H01L2924/0133 , H01L2924/12042 , H05K1/11 , H05K3/06 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/0979 , H05K2203/0369 , H05K2203/0376 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/00
Abstract: A carrier substrate includes an insulation layer, conductive towers and a circuit structure layer. A diameter of each of the conductive towers is increased gradually from a top surface to a bottom surface, and the conductive towers include first conductive towers and second conductive towers surrounding the first conductive towers. The circuit structure layer is disposed on the insulation layer and includes at least one dielectric layer, at least two circuit layers and first conductive vias. Each of the second conductive towers correspondingly connects to at least two of the first conductive vias, and each of the first conductive towers correspondingly connects to one of the first conductive vias. An interface exists between the first conductive vias and the first and the second conductive towers.
Abstract translation: 载体基板包括绝缘层，导电塔和电路结构层。 每个导电塔的直径从顶表面逐渐增加到底表面，并且导电塔包括第一导电塔和围绕第一导电塔的第二导电塔。 电路结构层设置在绝缘层上，并且包括至少一个电介质层，至少两个电路层和第一导电通孔。 每个第二导电塔对应地连接到第一导电通孔中的至少两个，并且每个第一导电塔对应地连接到第一导电通孔之一。 在第一导电通孔和第一和第二导电塔之间存在界面。
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