公开(公告)号：US09408313B2

公开(公告)日：2016-08-02

申请号：US14174858

申请日：2014-02-07

Applicant: Unimicron Technology Corp.

Inventor： Chun-Ting Lin ,  Ying-Chih Chan

IPC: H05K1/11 ,  H05K3/40 ,  H05K3/06

CPC classification number: H05K3/4007 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81385 ,  H05K3/062 ,  H05K2201/0367 ,  H05K2201/0376 ,  Y10T29/49156 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A packaging substrate is provided, including a substrate body and conductive pillars. The substrate body has a first surface and a second surface opposite to the first surface. The first surface has a plurality of first conductive pads, and the second surface has a die attach area and a peripheral area surrounding the die attach area. The die attach area has a plurality of second conductive pads embedded therein, wherein top surfaces of the second conductive pads are exposed from the second surface, and the die attach area of the second surface is fully exposed. The conductive pillars are correspondingly disposed on the second conductive pads and have first ends and opposite second ends. The first ends are closer than the second ends from the second conductive pads, and the first ends have a width bigger than a width of the second ends. A fabricating method thereof is also provided.

Abstract translation: 提供了一种包装基板，包括基体和导电支柱。 基板主体具有与第一表面相对的第一表面和第二表面。 第一表面具有多个第一导电焊盘，第二表面具有管芯附着区域和围绕管芯附着区域的周边区域。 管芯附着区域具有嵌入其中的多个第二导电焊盘，其中第二导电焊盘的顶表面从第二表面露出，并且第二表面的管芯附着区域被完全暴露。 导电柱相应地设置在第二导电焊盘上并且具有第一端和相对的第二端。 第一端比第二导电焊盘更靠近第二端，并且第一端的宽度大于第二端的宽度。 还提供了其制造方法。

公开(公告)号：US20160113114A1

公开(公告)日：2016-04-21

申请号：US14977669

申请日：2015-12-22

Applicant: Unimicron Technology Corp.

Inventor： Ying-Chih Chan ,  Chun-Ting Lin

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K3/4015 ,  H05K3/0097 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/041 ,  H05K2203/1536

Abstract: A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings exposing the first circuit layer. The conductive blocks fill the first openings and connect with the first circuit layer. A top surface of each of the conductive blocks is higher than the third surface of the insulation layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.

Abstract translation: 载体基板包括电介质层，第一电路层，绝缘层，导电块和第一导电结构。 电介质层具有第一表面，第二表面和盲孔。 第一电路层嵌入在第一表面中，盲孔从第二表面延伸到第一电路层。 绝缘层设置在第一表面上，并且具有第三表面，第四表面和暴露第一电路层的第一开口。 导电块填充第一开口并与第一电路层连接。 每个导电块的顶表面高于绝缘层的第三表面。 第一导电结构包括填充盲通孔的导电通孔和设置在第二表面的一部分上的第二电路层。

公开(公告)号：US09491871B2

公开(公告)日：2016-11-08

申请号：US14977669

申请日：2015-12-22

Applicant: Unimicron Technology Corp.

Inventor： Ying-Chih Chan ,  Chun-Ting Lin

IPC: H05K1/00 ,  H05K3/40 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K3/4015 ,  H05K3/0097 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/041 ,  H05K2203/1536

Abstract: A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings exposing the first circuit layer. The conductive blocks fill the first openings and connect with the first circuit layer. A top surface of each of the conductive blocks is higher than the third surface of the insulation layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.

Abstract translation: 载体基板包括电介质层，第一电路层，绝缘层，导电块和第一导电结构。 电介质层具有第一表面，第二表面和盲孔。 第一电路层嵌入在第一表面中，盲孔从第二表面延伸到第一电路层。 绝缘层设置在第一表面上，并且具有第三表面，第四表面和暴露第一电路层的第一开口。 导电块填充第一开口并与第一电路层连接。 每个导电块的顶表面高于绝缘层的第三表面。 第一导电结构包括填充盲通孔的导电通孔和设置在第二表面的一部分上的第二电路层。