公开(公告)号：US10529589B2

公开(公告)日：2020-01-07

申请号：US15995173

申请日：2018-06-01

申请人： Tokyo Electron Limited

发明人： Erdinc Karakas ,  Li Wang ,  Andrew Nolan ,  Christopher Talone ,  Shyam Sridhar ,  Alok Ranjan ,  Hiroto Ohtake

IPC分类号： H01L21/3213 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/033 ,  H01L21/027

摘要： A method of etching is described. The method providing a substrate having a first material composed of silicon-containing organic material and a second material that is different from the first material, forming a chemical mixture by plasma-excitation of a process gas containing SF6 and an optional inert gas, controlling a processing pressure at or above 100 mtorr, and exposing the first material on the substrate to the chemical mixture to selectively etch the first material relative to the second material.

公开(公告)号：US20200273992A1

公开(公告)日：2020-08-27

申请号：US16782680

申请日：2020-02-05

申请人： Tokyo Electron Limited

发明人： Sergey Voronin ,  Christopher Catano ,  Sang Cheol Han ,  Shyam Sridhar ,  Yusuke Yoshida ,  Christopher Talone ,  Alok Ranjan

IPC分类号： H01L29/78 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/3065

摘要： Residue at the base of a feature in a substrate to be etched is limited so that improved profiles may be obtained when forming vertical, narrow pitch, high aspect ratio features, for example fin field effect transistor (FinFET) gates. A thin bottom layer of the feature is formed of a different material than the main layer of the feature. The bottom material may be comprised of a material that preferentially etches and/or preferentially oxidizes as compared to the main layer. The bottom layer may comprise silicon germanium. The preferential etching characteristics may provide a process in which un-etched residuals do not remain. Even if residuals remain, after etch of the feature, an oxidation process may be performed. Enhanced oxidation rates of the bottom material allow any remaining residual to be oxidized. Plasma oxidation may be used. The oxidized material may then be removed by utilizing standard oxide removal mechanisms.

公开(公告)号：US20190259623A1

公开(公告)日：2019-08-22

申请号：US16277760

申请日：2019-02-15

申请人： Tokyo Electron Limited

发明人： Shyam Sridhar ,  Nayoung Bae ,  Sergey Voronin ,  Alok Ranjan

IPC分类号： H01L21/3065 ,  H01L21/311 ,  H01L21/3213

摘要： Sidewall etching of substrate features may be achieved by employing an etch stop layer formed over the features. The etch stop layer is thinner on sidewalls of the features as compared to the bottom of the features. The lateral etching of the features is achieved by use of an over etch which breaks through the etch stop layer on the sidewalls of the features but does not break through the etch stop layer formed at the bottom of the features. The use of the etch stop layer allows for lateral etching while preventing unwanted vertical etching. The lateral etching may be desirable for use in a number of structures, including but not limited to 3D structures. The lateral etching may also be used to provide vertical sidewalls by reducing the sidewall taper angle.

公开(公告)号：US20240363310A1

公开(公告)日：2024-10-31

申请号：US18308877

申请日：2023-04-28

申请人： Tokyo Electron Limited

发明人： Qiang Wang ,  Michael Hummel ,  Peter Lowell George Ventzek ,  Shyam Sridhar ,  Mitsunori Ohata

IPC分类号： H01J37/32 ,  H01Q5/10

CPC分类号： H01J37/32183 ,  H01J37/32091 ,  H01Q5/10

摘要： According to an embodiment, a plasma processing system includes a plasma chamber, an RF source, a matching circuit, a balun, and a resonating antenna. The resonating antenna includes a first and a second spiral resonant antenna (SRA), each having an electrical length corresponding to a quarter of a wavelength of a frequency of a forward RF wave generated by the RF source. The first end of the first SRA is coupled to a first balanced terminal of the balun and the second end of the first SRA is open circuit. The first end of the second SRA is coupled to a second balanced terminal of the balun and the second end of the second SRA is open circuit. The first and the second SRA are arranged in a symmetrically nested configuration having a same center point.

公开(公告)号：US20220059765A1

公开(公告)日：2022-02-24

申请号：US16999441

申请日：2020-08-21

申请人： Tokyo Electron Limited ,  SUNY Polytechnic Institute, College of Nanoscience and Engineering

发明人： Sergey Voronin ,  Qi Wang ,  Shyam Sridhar ,  Karsten Beckmann ,  Martin Rodgers ,  Nathaniel Cady

IPC分类号： H01L45/00

摘要： The performance of a ReRAM structure may be stabilized by utilizing a dry chemical gas removal (or cleaning) process to remove sidewall residue and/or etch by-products after etching the ReRAM stack layers. The dry chemical gas removal process decreases undesirable changes in the ReRAM forming voltage that may result from such sidewall residue and/or etch by-products. Specifically, the dry chemical gas removal process may reduce the ReRAM forming voltage that may otherwise result in a ReRAM structure that has the sidewall residue and/or etch by-products. In one embodiment, the dry chemical gas removal process may comprise utilizing a combination of HF and NH3 gases. The dry chemical gas removal process utilizing HF and NH3 gases may be particularly suited for removing halogen containing sidewall residue and/or etch by-products.

公开(公告)号：US20180358233A1

公开(公告)日：2018-12-13

申请号：US15995173

申请日：2018-06-01

申请人： Tokyo Electron Limited

发明人： Erdinc Karakas ,  Li Wang ,  Andrew Nolan ,  Christopher Talone ,  Shyam Sridhar ,  Alok Ranjan ,  Hiroto Ohtake

IPC分类号： H01L21/311 ,  H01L21/3065 ,  H01L21/3213

CPC分类号： H01L21/32137 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144

摘要： A method of etching is described. The method providing a substrate having a first material composed of silicon-containing organic material and a second material that is different from the first material, forming a chemical mixture by plasma-excitation of a process gas containing SF6 and an optional inert gas, controlling a processing pressure at or above 100 mtorr, and exposing the first material on the substrate to the chemical mixture to selectively etch the first material relative to the second material.

公开(公告)号：US20240339297A1

公开(公告)日：2024-10-10

申请号：US18296944

申请日：2023-04-06

申请人： Tokyo Electron Limited

发明人： Qiang Wang ,  Peter Lowell George Ventzek ,  Shyam Sridhar ,  Mitsunori Ohata

IPC分类号： H01J37/32 ,  H03H7/38

CPC分类号： H01J37/32183 ,  H01J37/32091 ,  H01J37/3211 ,  H03H7/38 ,  H01J37/32155 ,  H01J2237/24564 ,  H01J2237/334

摘要： An embodiment matching circuit for a plasma tool includes an impedance matching network configured to be coupled between a power supply and an antenna of a plasma chamber. The power supply is configured to provide power to and excite the antenna at a first frequency to generate a plasma. The impedance matching network is configured such that, during operation of the plasma chamber at the first frequency, a phase angle between a voltage and a current in the impedance matching network is matched to be 0°, and an impedance of the impedance matching network and the plasma chamber equals an impedance of the power supply. The impedance matching network includes a first adjustable reactive component; and a first fixed-length transmission line coupled between the first adjustable reactive component and an input of the antenna.

公开(公告)号：US20230377849A1

公开(公告)日：2023-11-23

申请号：US17841443

申请日：2022-06-15

申请人： Tokyo Electron Limited

发明人： Shyam Sridhar ,  Ya-Ming Chen ,  Peter Lowell George Ventzek ,  Mitsunori Ohata ,  Alok Ranjan

IPC分类号： H01J37/32 ,  H01L21/3065 ,  H01L21/311

CPC分类号： H01J37/32449 ,  H01J37/32146 ,  H01L21/3065 ,  H01L21/31116 ,  H01J2237/3343 ,  H01J2237/332

摘要： A method of processing a substrate that includes: loading the substrate in a plasma processing chamber, the substrate including an underlying layer; maintaining a steady state flow of a process gas into the plasma processing chamber in the plasma processing chamber; generating a plasma in the plasma processing chamber; exposing the substrate to the plasma to etch the underlying layer; and pulsing a first additional gas, using a first effusive gas injector, towards a first region of the substrate to disrupt the steady state flow of the process gas over the first region, the pulsing locally changing a composition of the plasma near the first region.

公开(公告)号：US10115591B2

公开(公告)日：2018-10-30

申请号：US15440604

申请日：2017-02-23

申请人： Tokyo Electron Limited

发明人： Shyam Sridhar ,  Li Wang ,  Andrew Nolan ,  Hiroto Ohtake ,  Sergey Voronin ,  Alok Ranjan

IPC分类号： H01L21/461 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/033 ,  H01L21/02

摘要： Methods and systems for selective silicon anti-reflective coating (SiARC) removal are described. An embodiment of a method includes providing a substrate in a process chamber, the substrate comprising: a resist layer, a SiARC layer, a pattern transfer layer, and an underlying layer. Such a method may also include performing a pattern transfer process configured to remove the resist layer and create a structure on the substrate, the structure comprising portions of the SiARC layer and the pattern transfer layer. The method may additionally include performing a modification process on the SiARC layer of the structure, the modification converting the SiARC layer into a porous SiARC layer. Further, the method may include performing a removal process of the porous SiARC layer of the structure, wherein the modification and removal processes of the SiARC layer are configured to meet target integration objectives.

公开(公告)号：US20180197730A1

公开(公告)日：2018-07-12

申请号：US15440604

申请日：2017-02-23

申请人： Tokyo Electron Limited

发明人： Shyam Sridhar ,  Li Wang ,  Andrew Nolan ,  Hiroto Ohtake ,  Sergey Voronin ,  Alok Ranjan

IPC分类号： H01L21/027 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/033

CPC分类号： H01L21/0274 ,  H01L21/02126 ,  H01L21/02315 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/0272 ,  H01L21/0276 ,  H01L21/0331 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/66742

摘要： Methods and systems for selective silicon anti-reflective coating (SiARC) removal are described. An embodiment of a method includes providing a substrate in a process chamber, the substrate comprising: a resist layer, a SiARC layer, a pattern transfer layer, and an underlying layer. Such a method may also include performing a pattern transfer process configured to remove the resist layer and create a structure on the substrate, the structure comprising portions of the SiARC layer and the pattern transfer layer. The method may additionally include performing a modification process on the SiARC layer of the structure, the modification converting the SiARC layer into a porous SiARC layer. Further, the method may include performing a removal process of the porous SiARC layer of the structure, wherein the modification and removal processes of the SiARC layer are configured to meet target integration objectives.