公开(公告)号：US08218518B2

公开(公告)日：2012-07-10

申请号：US11750742

申请日：2007-05-18

Applicant: Eran Pisek ,  Thomas M. Henige

Inventor： Eran Pisek ,  Thomas M. Henige

IPC: H04B7/216

CPC classification number: H04L1/0055 ,  H03M13/27 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/6519 ,  H04L1/0071

Abstract: A software-defined radio (SDR) system that operates under a plurality of wireless communication standards. The SDR system comprises a reconfigurable maximum aposteriori probability (MAP) decoder capable of being configured under software control to decode a received data block according to a select wireless communication standard and a reconfigurable interleaver associated with the reconfigurable MAP decoder. The reconfigurable interleaver comprises a reconfigurable interleaver core circuitry capable of being configured under software control to operate according to the selected wireless communication standard and a unified interleaver interface for coupling a defined set of control and bus signals from the reconfigurable MAP decoder to the reconfigurable interleaver core circuitry.

Abstract translation: 一种在多种无线通信标准下工作的软件定义无线电（SDR）系统。 SDR系统包括可配置在软件控制下的可重配置最大后验概率（MAP）解码器，以根据选择无线通信标准对接收到的数据块进行解码，以及与可重新配置的MAP解码器相关联的可重配置交织器。 可重配置交织器包括能够被配置在软件控制下以根据所选择的无线通信标准进行操作的可重配置交织器核心电路和统一的交织器接口，用于将定义的一组控制和总线信号从可重新配置的MAP解码器耦合到可重配置交织器核心 电路。

公开(公告)号：US09264073B2

公开(公告)日：2016-02-16

申请号：US13595846

申请日：2012-08-27

Applicant: Mehrzad Malmirchegini ,  Shadi Abu-surra ,  Thomas M. Henige ,  Eran Pisek

Inventor： Mehrzad Malmirchegini ,  Shadi Abu-surra ,  Thomas M. Henige ,  Eran Pisek

IPC: H03M13/05 ,  G06F11/10 ,  H03M13/11 ,  H03M13/00 ,  H03M13/31

CPC classification number: H03M13/116 ,  G06F11/1008 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1165 ,  H03M13/118 ,  H03M13/31 ,  H03M13/6544 ,  H03M13/6577 ,  H03M13/658 ,  H03M13/6591

Abstract: A low-density parity check (LDPC) decoder includes a memory configured to store multiple variable node LLR values in a LLR memory and multiple check nodes messages in a CN memory. The LDPC decoder also includes a saturation indicator configured to determine whether each check node of the H-matrix becomes saturated, and a multiplexer. The multiplexer is configured store an extrinsic check node value in the CN memory and updated LLR value in the LLR memory when the variable node is not saturated; and store a freeze input value in the CN memory and a freeze value in the LLR memory when the variable node is saturated.

Abstract translation: 低密度奇偶校验（LDPC）解码器包括被配置为在LLR存储器中存储多个可变节点LLR值的存储器和CN存储器中的多个校验节点消息。 LDPC解码器还包括饱和指示符，其被配置为确定H矩阵的每个校验节点是否饱和，以及多路复用器。 当变量节点不饱和时，多路复用器被配置为在CN存储器中存储外部校验节点值并在LLR存储器中存储更新的LLR值; 并且当可变节点饱和时，将冻结输入值存储在CN存储器中并在LLR存储器中存储冻结值。

公开(公告)号：US08417756B2

公开(公告)日：2013-04-09

申请号：US12216896

申请日：2008-07-11

Applicant: Eran Pisek ,  Thomas M. Henige

Inventor： Eran Pisek ,  Thomas M. Henige

IPC: G06F7/38

CPC classification number: G06F7/728

Abstract: A method of a hardware based Montgomery reduction contemplates preparing a table comprising a plurality of sets of values of 2K+i (mod n), 2K+i+1 (mod n) and (2K+i+2K+i+1)(mod n), where i=0 to M−2, n is a modulo number, K is an integer, and M is a number of significant bits in a binary Y; selecting one of the values within one of the plurality of sets of the table in dependence upon a value of two neighboring bits Yi+1,i of the binary Y; adding two neighboring selected values and calculating the modulo value of the sum value with the modulo number n; repeatedly adding two neighboring calculated modulo values and calculating the modulo value of the intermediate sum of the two neighboring calculated modulo values until only a single calculated module value is obtained; and setting the single value as the Montgomery representation.

Abstract translation: 一种基于硬件的Montgomery减少方法考虑准备包括多个值的组2K + i（mod n），2K + i + 1（mod n）和（2K + i + 2K + i + 1）（ mod n），其中i = 0到M-2，n是模数，K是整数，M是二进制Y中的有效位数; 根据二进制Y的两个相邻位Yi + 1，i的值，选择该表的多个集合之一内的值之一; 加上两个相邻的选择值，并用模数n计算求和值的模数; 反复添加两个相邻的计算的模数值，并计算两个相邻计算的模数值的中间和的模数，直到仅获得单个计算的模块值; 并将单个值设置为蒙哥马利表示。

公开(公告)号：US20130061114A1

公开(公告)日：2013-03-07

申请号：US13595846

申请日：2012-08-27

Applicant: Mehrzad Malmirchegini ,  Shadi Abu-Surra ,  Thomas M. Henige ,  Eran Pisek

Inventor： Mehrzad Malmirchegini ,  Shadi Abu-Surra ,  Thomas M. Henige ,  Eran Pisek

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/116 ,  G06F11/1008 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1165 ,  H03M13/118 ,  H03M13/31 ,  H03M13/6544 ,  H03M13/6577 ,  H03M13/658 ,  H03M13/6591

Abstract: A low-density parity check (LDPC) decoder includes a memory configured to store multiple variable node LLR values in a LLR memory and multiple check nodes messages in a CN memory. The LDPC decoder also includes a saturation indicator configured to determine whether each check node of the H-matrix becomes saturated, and a multiplexer. The multiplexer is configured store an extrinsic check node value in the CN memory and updated LLR value in the LLR memory when the variable node is not saturated; and store a freeze input value in the CN memory and a freeze value in the LLR memory when the variable node is saturated.

Abstract translation: 低密度奇偶校验（LDPC）解码器包括被配置为在LLR存储器中存储多个可变节点LLR值的存储器和CN存储器中的多个校验节点消息。 LDPC解码器还包括饱和指示符，其被配置为确定H矩阵的每个校验节点是否饱和，以及多路复用器。 当变量节点不饱和时，多路复用器被配置为在CN存储器中存储外部校验节点值并在LLR存储器中存储更新的LLR值; 并且当可变节点饱和时，将冻结输入值存储在CN存储器中并在LLR存储器中存储冻结值。

公开(公告)号：US07895497B2

公开(公告)日：2011-02-22

申请号：US11605525

申请日：2006-11-29

Applicant: Eran Pisek ,  Thomas M. Henige

Inventor： Eran Pisek ,  Thomas M. Henige

IPC: H03M13/00

CPC classification number: H04L1/0055 ,  H03M13/2969 ,  H03M13/3905 ,  H03M13/3911 ,  H03M13/3972 ,  H03M13/3983 ,  H03M13/6569 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0057 ,  H04L1/0066

Abstract: A maximum a posteriori probability (MAP) block decoder for decoding a received data block of input samples. The MAP block decoder segments the received data block into at least a first segment and a second segment and calculates and stores alpha values during forward processing of the first segment. The MAP block decoder uses a first selected alpha value calculated during forward processing of the first segment as initial state information during forward processing of the second segment. The first and second segments may overlap each other, such that the last M samples of the first segment are the same as the first M samples of the second segment.

Abstract translation: 用于对输入样本的接收数据块进行解码的最大后验概率（MAP）块解码器。 MAP块解码器将接收的数据块分段成至少第一段和第二段，并且在第一段的正向处理期间计算并存储α值。 MAP块解码器使用在第一段的正向处理期间计算的第一选择的α值作为第二段的正向处理期间的初始状态信息。 第一和第二段可以彼此重叠，使得第一段的最后M个样本与第二段的前M个样本相同。

公开(公告)号：US20080003949A1

公开(公告)日：2008-01-03

申请号：US11655471

申请日：2007-01-19

Applicant: Thirumalarao Voonna ,  Jasmin Oz ,  Eran Pisek ,  Thomas M. Henige

Inventor： Thirumalarao Voonna ,  Jasmin Oz ,  Eran Pisek ,  Thomas M. Henige

IPC: H04B17/00

CPC classification number: H04B17/0085

Abstract: A method for testing a software-defined radio (SDR) device is provided. The method includes configuring the SDR device for a first standard. A first test is performed on the SDR device under the first standard. Test data for the first test is received from the SDR device. A switching time for configuring the SDR device for the first standard is determined based on the test data for the first test.

Abstract translation: 提供了一种用于测试软件定义无线电（SDR）设备的方法。 该方法包括为第一标准配置SDR设备。 在第一个标准的SDR设备上执行第一个测试。 从SDR设备接收第一次测试的测试数据。 基于第一测试的测试数据来确定用于配置用于第一标准的SDR设备的切换时间。

公开(公告)号：US09634693B2

公开(公告)日：2017-04-25

申请号：US13248900

申请日：2011-09-29

Applicant: Eran Pisek ,  Shadi Abu-Surra ,  Thomas M. Henige

Inventor： Eran Pisek ,  Shadi Abu-Surra ,  Thomas M. Henige

IPC: H03M13/00 ,  H03M13/31 ,  H03M13/03 ,  H03M13/11

CPC classification number: H03M13/31 ,  H03M13/033 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/118

Abstract: An apparatus and method decode LDPC code. The apparatus includes a memory and a number of LDPC processing elements. The memory is configured to receive a LDPC codeword having a length equal to a lifting factor times a base LDPC code length, wherein the lifting factor is greater than one. The number of LDPC processing elements configured to decode the LDPC codeword, wherein each of the number of LDPC processing elements decode separate portions of the LDPC codeword.

公开(公告)号：US08627166B2

公开(公告)日：2014-01-07

申请号：US13306747

申请日：2011-11-29

Applicant: Shadi Abu-Surra ,  Thomas M. Henige ,  Eran Pisek ,  Zhouyue Pi

Inventor： Shadi Abu-Surra ,  Thomas M. Henige ,  Eran Pisek ,  Zhouyue Pi

IPC: H03M13/00

CPC classification number: H03M13/618 ,  H03M13/033 ,  H03M13/036 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/6516

Abstract: A method constructs a family of low-density-parity-check (LDPC) codes. The method includes identifying a code rate for an LDPC code in the family, identifying a protograph for the LDPC code, and constructing a base matrix for the LDPC code. The base matrix is constructed by replacing each zero in the protograph with a ‘−1’, selecting a corresponding value for an absolute shift for each one in the protograph based on constraining a number of relative shifts per column of the LDPC code to one and increasing a size of a smallest cycle in a graph of the LDPC code, and replacing each one in the protograph with the corresponding value.

Abstract translation: 一种方法构建了一系列低密度奇偶校验（LDPC）码。 该方法包括识别该系列中的LDPC码的码率，识别LDPC码的原型图，以及构造LDPC码的基本矩阵。 基本矩阵是通过用“-1”代替原型图中的每个零来构造的，基于将每个LDPC码的相对位移数量约束为1，为了对原型图中的每一个选择相应的绝对位移值， 增加LDPC码的图形中的最小周期的大小，并将原型图中的每一个替换为相应的值。

公开(公告)号：US08606259B2

公开(公告)日：2013-12-10

申请号：US11655471

申请日：2007-01-19

Applicant: Thirumalarao Voonna ,  Jasmin Oz ,  Eran Pisek ,  Thomas M. Henige

Inventor： Thirumalarao Voonna ,  Jasmin Oz ,  Eran Pisek ,  Thomas M. Henige

IPC: H04W24/00

CPC classification number: H04B17/0085

Abstract: A method for testing a software-defined radio (SDR) device is provided. The method includes configuring the SDR device for a first standard. A first test is performed on the SDR device under the first standard. Test data for the first test is received from the SDR device. A switching time for configuring the SDR device for the first standard is determined based on the test data for the first test.

Abstract translation: 提供了一种用于测试软件定义无线电（SDR）设备的方法。 该方法包括为第一标准配置SDR设备。 在第一个标准的SDR设备上执行第一个测试。 从SDR设备接收第一次测试的测试数据。 基于第一测试的测试数据来确定用于配置用于第一标准的SDR设备的切换时间。

公开(公告)号：US20120240001A1

公开(公告)日：2012-09-20

申请号：US13306747

申请日：2011-11-29

Applicant: Shadi Abu-Surra ,  Thomas M. Henige ,  Eran Pisek ,  Zhouyue Pi

Inventor： Shadi Abu-Surra ,  Thomas M. Henige ,  Eran Pisek ,  Zhouyue Pi

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/618 ,  H03M13/033 ,  H03M13/036 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/6516

Abstract: A method constructs a family of low-density-parity-check (LDPC) codes. The method includes identifying a code rate for an LDPC code in the family, identifying a protograph for the LDPC code, and constructing a base matrix for the LDPC code. The base matrix is constructed by replacing each zero in the protograph with a ‘−1’, selecting a corresponding value for an absolute shift for each one in the protograph based on constraining a number of relative shifts per column of the LDPC code to one and increasing a size of a smallest cycle in a graph of the LDPC code, and replacing each one in the protograph with the corresponding value.

Abstract translation: 一种方法构建了一系列低密度奇偶校验（LDPC）码。 该方法包括识别该系列中的LDPC码的码率，识别LDPC码的原型图，以及构造LDPC码的基本矩阵。 基本矩阵是通过用“-1”代替原型图中的每个零来构造的，基于将每个LDPC码的相对位移数量约束为1，为了对原型图中的每一个选择相应的绝对位移值， 增加LDPC码的图形中的最小周期的大小，并将原型图中的每一个替换为相应的值。