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    HIGH RELIABILITY POLYSILICON COMPONENTS
    1.
    发明申请
    HIGH RELIABILITY POLYSILICON COMPONENTS 审中-公开

    公开(公告)号：US20200075583A1

    公开(公告)日：2020-03-05

    申请号：US16118648

    申请日：2018-08-31

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

    IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L49/02 ,  G06F17/50

    摘要： The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

    High reliability polysilicon components
    2.
    发明授权
    High reliability polysilicon components 有权

    公开(公告)号：US11296075B2

    公开(公告)日：2022-04-05

    申请号：US16118648

    申请日：2018-08-31

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Robert M. Higgins ,  Henry Litzmann Edwards ,  Xiaoju Wu ,  Shariq Arshad ,  Li Wang ,  Jonathan Philip Davis ,  Tathagata Chatterjee

    IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  G06F30/392

    摘要： The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

    Selective etches for reducing cone formation in shallow trench isolations
    3.
    发明授权
    Selective etches for reducing cone formation in shallow trench isolations 有权

    公开(公告)号：US11171035B2

    公开(公告)日：2021-11-09

    申请号：US16567661

    申请日：2019-09-11

    申请人： Texas Instruments Incorporated

    发明人： Karen Hildegard Ralston Kirmse ,  Jonathan Philip Davis

    IPC分类号： H01L21/762 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3065

    摘要： Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

    SELECTIVE ETCHES FOR REDUCING CONE FORMATION IN SHALLOW TRENCH ISOLATIONS
    4.
    发明公开
    SELECTIVE ETCHES FOR REDUCING CONE FORMATION IN SHALLOW TRENCH ISOLATIONS 审中-公开

    公开(公告)号：US20240105501A1

    公开(公告)日：2024-03-28

    申请号：US18530423

    申请日：2023-12-06

    申请人： Texas Instruments Incorporated

    发明人： Karen Hildegard Ralston Kirmse ,  Jonathan Philip Davis

    IPC分类号： H01L21/762 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/06

    CPC分类号： H01L21/76229 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L29/0649

    摘要： Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

    Selective etches for reducing cone formation in shallow trench isolations
    6.
    发明授权
    Selective etches for reducing cone formation in shallow trench isolations 有权

    公开(公告)号：US11908729B2

    公开(公告)日：2024-02-20

    申请号：US17478306

    申请日：2021-09-17

    申请人： Texas Instruments Incorporated

    发明人： Karen Hildegard Ralston Kirmse ,  Jonathan Philip Davis

    IPC分类号： H01L21/762 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3065

    CPC分类号： H01L21/76229 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/0649

    摘要： Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

    SELECTIVE ETCHES FOR REDUCING CONE FORMATION IN SHALLOW TRENCH ISOLATIONS
    7.
    发明申请
    SELECTIVE ETCHES FOR REDUCING CONE FORMATION IN SHALLOW TRENCH ISOLATIONS 有权

    公开(公告)号：US20220005729A1

    公开(公告)日：2022-01-06

    申请号：US17478306

    申请日：2021-09-17

    申请人： Texas Instruments Incorporated

    发明人： Karen Hildegard Ralston Kirmse ,  Jonathan Philip Davis

    IPC分类号： H01L21/762 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/3065

    摘要： Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

    SELECTIVE ETCHES FOR REDUCING CONE FORMATION IN SHALLOW TRENCH ISOLATIONS
    9.
    发明申请
    SELECTIVE ETCHES FOR REDUCING CONE FORMATION IN SHALLOW TRENCH ISOLATIONS 审中-公开

    公开(公告)号：US20190198382A1

    公开(公告)日：2019-06-27

    申请号：US15852171

    申请日：2017-12-22

    申请人： Texas Instruments Incorporated

    发明人： Karen Hildegard Ralston Kirmse ,  Jonathan Philip Davis

    IPC分类号： H01L21/762 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311

    摘要： Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.