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    Multi-bank synchronous semiconductor memory device
    1.
    发明授权
    Multi-bank synchronous semiconductor memory device 失效
    多组同步半导体存储器件

    公开(公告)号：US5764584A

    公开(公告)日：1998-06-09

    申请号：US900650

    申请日：1997-07-25

    Applicant: Takahiko Fukiage ,  Mikio Sakurai ,  Yasuhiro Konishi

    Inventor： Takahiko Fukiage ,  Mikio Sakurai ,  Yasuhiro Konishi

    IPC: G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00 ,  G11C7/00

    CPC classification number: G11C7/103 ,  G11C7/1072

    Abstract: A read register and a data transfer circuit are provided to implement two separate data transfer paths with respect to a preamplifier, for alternately transferring data through these two paths. Thus, the data can be transferred with no data collision in each clock cycle. The data are transferred at a high speed every clock cycle regardless of the bank number and the CAS latency in a multi-bank synchronous memory device.

    Abstract translation: 提供读寄存器和数据传输电路以实现关于前置放大器的两个单独的数据传输路径，用于通过这两个路径交替地传送数据。 因此，可以在每个时钟周期内数据传输而没有数据冲突。 数据在每个时钟周期以高速传输，而不管多行同步存储器件中的存储体号和CAS延迟。

    Voltage generating circuit for semiconductor device
    4.
    发明授权
    Voltage generating circuit for semiconductor device 失效
    半导体器件用电压发生电路

    公开(公告)号：US5008609A

    公开(公告)日：1991-04-16

    申请号：US526740

    申请日：1990-05-22

    Applicant: Takahiko Fukiage

    Inventor： Takahiko Fukiage

    IPC: H01L27/04 ,  G05F1/618 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  H01L21/822

    CPC classification number: G05F3/24 ,  G11C5/147

    Abstract: In an output stage, an n-FET and a p-FET are connected in series, which is interposed between a power supply line and a ground. A first serial connection circuit generates a gate potential of the n-FET, and a second serial connection circuit generates a gate potential of the p-FET. The first and the second serial connection circuits are connected in parallel to each other, each of which has its one end connected to the power supply line through a resistor, and its other end connected to the ground through a resistor. As a result, even if a resistance value of the resistor is small, currents to be consumed can be reduced.

    Abstract translation: 在输出级中，n-FET和p-FET串联连接在电源线和地之间。 第一串行连接电路产生n-FET的栅极电位，第二串联连接电路产生p-FET的栅极电位。 第一和第二串行连接电路彼此并联连接，每个电路的一端通过电阻连接到电源线，另一端通过电阻连接到地。 结果，即使电阻器的电阻值小，可以减少要消耗的电流。

    Semiconductor device performing serial parallel conversion
    5.
    发明授权
    Semiconductor device performing serial parallel conversion 有权
    执行串行并行转换的半导体器件

    公开(公告)号：US08259526B2

    公开(公告)日：2012-09-04

    申请号：US12627768

    申请日：2009-11-30

    Applicant: Takahiko Fukiage ,  Atsushi Shimizu

    Inventor： Takahiko Fukiage ,  Atsushi Shimizu

    IPC: G11C7/00

    CPC classification number: G11C11/4076 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/005 ,  G11C2207/107

    Abstract: A first transfer circuit includes pipeline circuits having different number of stages, and switch circuits that exclusively supply the pipeline circuits with first and second read data. A second transfer circuit includes pipeline circuits having different number of stages, and switch circuits that exclusively supply the pipeline circuits with third and fourth read data. Outputs of the first and second transfer circuits are sequentially output from a multiplex circuit. When a first operation mode is selected, all the pipeline circuits are activated. When a second operation mode is selected, one of the pipeline circuits in the first transfer circuit and one of the pipeline circuits in the second transfer circuit are activated, whereas the others of the pipeline circuits are inactivated.

    Abstract translation: 第一传输电路包括具有不同级数的流水线电路，以及专门为流水线电路提供第一和第二读取数据的开关电路。 第二传输电路包括具有不同级数的流水线电路，以及专门为流水线电路提供第三和第四读取数据的开关电路。 从多路复用电路依次输出第一和第二传输电路的输出。 当选择第一操作模式时，所有流水线电路都被激活。 当选择第二操作模式时，第一传送电路中的流水线电路和第二传送电路中的一个流水线电路中的一个被激活，而其他流水线电路被去激活。

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20100195413A1

    公开(公告)日：2010-08-05

    申请号：US12700121

    申请日：2010-02-04

    Applicant: Atsushi SHIMIZU ,  Takahiko Fukiage

    Inventor： Atsushi SHIMIZU ,  Takahiko Fukiage

    IPC: G11C7/10 ,  G11C7/00

    CPC classification number: G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/1069

    Abstract: To provide a semiconductor memory device including a mode register in which a mode signal is set, a data amplifier that amplifies read data read from a memory cell array, a data bus onto which the read data amplified by the data amplifier is transmitted, a data input/output circuit that outputs a signal on the data bus to outside, and a mode signal output circuit that outputs the mode signal set in the mode register onto the data bus. Because the mode signal is not caused to interrupt halfway along the data input/output circuit, but supplied onto the data bus that connects the data amplifier to the data input/output circuit, no collision of the read data with the mode signal occurs in the data input/output circuit.

    Abstract translation: 为了提供包括其中设置有模式信号的模式寄存器的半导体存储器件，放大从存储单元阵列读出的读取数据的数据放大器，由数据放大器放大的读取数据被发送到的数据总线，数据 将数据总线上的信号输出到外部的输入/输出电路以及将模式寄存器中设置的模式信号输出到数据总线上的模式信号输出电路。 由于模式信号不是沿着数据输入/输出电路中途中断，而是提供给连接数据放大器到数据输入/输出电路的数据总线，不会在读取数据与模式信号之间发生冲突 数据输入/输出电路。

    Semiconductor memory device with changeable input/output data bit arrangement
    7.
    发明授权
    Semiconductor memory device with changeable input/output data bit arrangement 失效
    具有可变输入/输出数据位布置的半导体存储器件

    公开(公告)号：US5400292A

    公开(公告)日：1995-03-21

    申请号：US155369

    申请日：1993-11-22

    Applicant: Takahiko Fukiage ,  Yoshinori Inoue

    Inventor： Takahiko Fukiage ,  Yoshinori Inoue

    IPC: G11C11/401 ,  G11C7/10 ,  G11C11/409 ,  G11C8/00

    CPC classification number: G11C7/1006 ,  G11C7/1045

    Abstract: A dynamic type semiconductor memory device includes a plurality of data input/output nodes, a plurality of /CAS buffers for generating column address strobe signals corresponding to each of said input/output nodes, and an input node carrying out only data input. A switching signal generation circuit generates first and second switching signals indicating data input/output control modes. Memory cells corresponding in number to the data input/output nodes are selected simultaneously from a memory cell array. In operation of control mode A, data input/output is effected using an input node and one data input/ouput node. In the case of control mode B, data writing/reading is effected via a plurality of data input/output nodes according to one column address strobe signal. In the case of control mode C, data input/output is carried out individually for each input/output node according to a plurality of column address strobe signals. Modes A, B and C can be realized in one DRAM. Particularly, in mode C controlling data input/output according to respective column address strobe signals, writing/reading of unnecessary data bits can be prevented to reduce power consumption and prevent erroneous parity bit writing.

    Abstract translation: 动态型半导体存储器件包括多个数据输入/输出节点，多个/ CAS缓冲器，用于产生与每个所述输入/输出节点对应的列地址选通信号，以及输入节点仅执行数据输入。 切换信号生成电路生成表示数据输入/输出控制模式的第一和第二切换信号。 从存储单元阵列同时选择与数据输入/输出节点相对应的存储单元。 在控制模式A的操作中，使用输入节点和一个数据输入/输出节点来实现数据输入/输出。 在控制模式B的情况下，根据一列地址选通信号通过多个数据输入/输出节点进行数据写/读。 在控制模式C的情况下，根据多个列地址选通信号，针对每个输入/输出节点分别执行数据输入/输出。 模式A，B和C可以在一个DRAM中实现。 特别地，在根据各列地址选通信号控制数据输入/输出的模式C中，可以防止写入/读取不必要的数据位，从而降低功耗并防止错误的奇偶校验位写入。

    Mode register output circuit
    8.
    发明授权
    Mode register output circuit 有权
    模式寄存器输出电路

    公开(公告)号：US08325537B2

    公开(公告)日：2012-12-04

    申请号：US12700121

    申请日：2010-02-04

    Applicant: Atsushi Shimizu ,  Takahiko Fukiage

    Inventor： Atsushi Shimizu ,  Takahiko Fukiage

    IPC: G11C7/10

    CPC classification number: G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/1069

    Abstract: To provide a semiconductor memory device including a mode register in which a mode signal is set, a data amplifier that amplifies read data read from a memory cell array, a data bus onto which the read data amplified by the data amplifier is transmitted, a data input/output circuit that outputs a signal on the data bus to outside, and a mode signal output circuit that outputs the mode signal set in the mode register onto the data bus. Because the mode signal is not caused to interrupt halfway along the data input/output circuit, but supplied onto the data bus that connects the data amplifier to the data input/output circuit, no collision of the read data with the mode signal occurs in the data input/output circuit.

    Abstract translation: 为了提供包括其中设置有模式信号的模式寄存器的半导体存储器件，放大从存储单元阵列读出的读取数据的数据放大器，由数据放大器放大的读取数据被发送到的数据总线，数据 将数据总线上的信号输出到外部的输入/输出电路以及将模式寄存器中设置的模式信号输出到数据总线上的模式信号输出电路。 由于模式信号不是沿着数据输入/输出电路中途中断，而是提供给连接数据放大器到数据输入/输出电路的数据总线，不会在读取数据与模式信号之间发生冲突 数据输入/输出电路。

    Semiconductor memory device with individual and selective refresh of data storage banks
    9.
    发明授权
    Semiconductor memory device with individual and selective refresh of data storage banks 有权
    半导体存储器件具有独立的选择刷新数据存储库

    公开(公告)号：US08094512B2

    公开(公告)日：2012-01-10

    申请号：US12685245

    申请日：2010-01-11

    Applicant: Takahiko Fukiage

    Inventor： Takahiko Fukiage

    IPC: G11C7/00

    CPC classification number: G11C11/406 ,  G11C11/40618

    Abstract: A conventional semiconductor memory device may be in need of a special refresh sequence if it is desired to reduce the current consumption in connection with a refresh operation. With this in view, there is disclosed a semiconductor memory device 1 that has a recording area 30 formed by a plurality of memory banks 31 to 3n. The refreshing operation for this semiconductor memory device 1 may be performed on the memory bank basis. The semiconductor memory device 1 includes refresh control circuits 21 to 2n and holding circuits 11 to 1n in association individually with the memory banks 31 to 3n. The holding circuits 11 to 1n are set when data has been written in associated ones of the memory banks 31 to 3n following resetting of the semiconductor memory device. The refresh control circuits 21 to 2n set the associated memory banks 31 to 3n to a refresh enabling state in case the associated holding circuits 11 to 1n are in a set state (FIG. 1).

    Abstract translation: 如果期望减少与刷新操作相关的电流消耗，传统的半导体存储器件可能需要特殊的刷新序列。 鉴于此，公开了具有由多个存储体31〜3n形成的记录区域30的半导体存储器件1。 该半导体存储器件1的刷新操作可以基于存储体执行。 半导体存储器件1包括与存储体31至3n相关联的刷新控制电路21至2n和保持电路11至1n。 在半导体存储器件复位之后，当数据被写入相关联的存储体31至3n中时，保持电路11至1n被置位​​。 刷新控制电路21至2n在关联的保持电路11至1n处于设置状态（图1）的情况下将相关联的存储体31至3n设置为刷新使能状态。

    Semiconductor memory device suppressing peak current
    10.
    发明授权
    Semiconductor memory device suppressing peak current 失效
    半导体存储器件抑制峰值电流

    公开(公告)号：US06801460B2

    公开(公告)日：2004-10-05

    申请号：US10654948

    申请日：2003-09-05

    Applicant: Takahiko Fukiage

    Inventor： Takahiko Fukiage

    IPC: G11C700

    CPC classification number: G11C11/4091 ,  G11C7/06 ,  G11C8/12 ,  G11C8/18 ,  G11C2207/065

    Abstract: In a semiconductor memory device including a plurality of memory chips, the plurality of memory chips are divided into first and second groups that are operated in parallel with each other at the time of a data read. Timings of activating sense amplifiers belonging to the first and second groups are made different from each other. Accordingly, the maximum value of peak current generated when the sense amplifiers are activated at the time of a data read is reduced by half in the semiconductor memory device as a whole. As the peak current is suppressed, the data reading operation can be executed stably.

    Abstract translation: 在包括多个存储器芯片的半导体存储器件中，多个存储器芯片被划分成在数据读取时彼此并行操作的第一和第二组。 激活属于第一和第二组的读出放大器的定时彼此不同。 因此，在半导体存储器件整体上读出放大器激活时产生的峰值电流的最大值减少了一半。 随着峰值电流被抑制，可以稳定地执行数据读取操作。

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