公开(公告)号：US5166082A

公开(公告)日：1992-11-24

申请号：US712713

申请日：1991-06-10

申请人： Takaharu Nakamura ,  Toshikazu Kuroda ,  Tatsuya Kimura

发明人： Takaharu Nakamura ,  Toshikazu Kuroda ,  Tatsuya Kimura

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/761 ,  H01L21/762 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

CPC分类号： H01L21/8249 ,  H01L21/761 ,  H01L21/76221 ,  H01L27/0623 ,  Y10S148/008 ,  Y10S148/009

摘要： This invention provides devices each of which has at least one bipolar transistor and at least one MOS transistor, both formed on a substrate. This invention also provides their fabrication process. Each device is constructed of epitaxial layers of a first and second conductivity types, surfaces of said epitaxial layers being partly exposed, at least one MOS transistor formed in the epitaxial layer of the first conductivity type, and at least one bipolar transistor formed in the epitaxial layer of the second conductivity type. Its fabrication process comprises the steps of forming the epitaxial layer of the second conductivity type on the semiconductor substrate, forming the epitaxial layer of the first conductivity type on a part of the epitaxial layer of the second conductivity type, forming the bipolar transistor in the epitaxial layer of the second conductivity type and then forming the MOS transistor in the epitaxial layer of the first conductivity type.

摘要翻译： 本发明提供了各自具有形成在基板上的至少一个双极晶体管和至少一个MOS晶体管的器件。 本发明还提供了它们的制造方法。 每个器件由第一和第二导电类型的外延层构成，所述外延层的表面部分暴露，形成在第一导电类型的外延层中的至少一个MOS晶体管和形成在外延层中的至少一个双极晶体管 第二导电类型的层。 其制造方法包括以下步骤：在半导体衬底上形成第二导电类型的外延层，在第二导电类型的外延层的一部分上形成第一导电类型的外延层，在外延层中形成双极晶体管 层，然后在第一导电类型的外延层中形成MOS晶体管。

公开(公告)号：US07498615B2

公开(公告)日：2009-03-03

申请号：US11276403

申请日：2006-02-28

申请人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

发明人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

IPC分类号： H01L29/74

CPC分类号： H01L27/0262

摘要： An electro-static discharge protection circuit includes a thyristor mode ensuring circuit and a thyristor rectifier circuit. The thyristor mode ensuring circuit includes a capacitive element connected between a higher potential line and a lower potential line, and ensures a constant and sufficient capacity independently of the number of input/output signal bits, even when the number of input/output signal bits is a theoretical minimum, i.e. 1, so that a surge current induced by electro-static discharge (ESD) applied to an output pad is injected into the first capacitive element to charge it. Thus, by means of the current caused by the surge current, the thyristor rectifier circuit is triggered into a thyristor mode, which allows the surge current to flow to the lower potential line through the thyristor rectifier circuit, protecting circuitry against the surge current.

摘要翻译： 一种静电放电保护电路包括晶闸管模式保护电路和晶闸管整流电路。 晶闸管模式确保电路包括连接在较高电位线和下电位线之间的电容元件，并且即使当输入/输出信号位的数量为 理论最小值，即1，使得由施加到输出焊盘的静电放电（ESD）引起的浪涌电流被注入到第一电容元件中以对其充电。 因此，通过由浪涌电流引起的电流，晶闸管整流电路被触发成晶闸管模式，这允许浪涌电流通过晶闸管整流电路流向下电位线，保护电路免受浪涌电流的影响。

公开(公告)号：US20050035416A1

公开(公告)日：2005-02-17

申请号：US10947329

申请日：2004-09-23

申请人： Toshikazu Kuroda ,  Katsuhito Sasaki

发明人： Toshikazu Kuroda ,  Katsuhito Sasaki

IPC分类号： H01L23/528 ,  H01L23/58 ,  H01L23/60 ,  H01L23/62 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L23/5286 ,  H01L23/585 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/41725 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.

摘要翻译： 同心多边形金属氧化物半导体场效应晶体管被设计为避免中心漏极扩散的角和周围环形栅电极的内角之间的重叠。 例如，可以通过消除角部来减小栅电极来分离直线段。 或者，漏极扩散可以具有十字形状，并且外部环形源极扩散可以被减小到面向十字的端部的直线段，或者源极和漏极扩散和栅电极可以全部被减小以分离直线段。 通过避免角区域的电场集中，这些设计提供了增强的防静电放电保护。

公开(公告)号：US07723794B2

公开(公告)日：2010-05-25

申请号：US11516752

申请日：2006-09-07

申请人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

发明人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L27/0288 ,  Y10T436/206664

摘要： A load driving device includes a drive control signal generation circuit generating a load drive control signal and a semiconductor buffer circuit generating an output signal in response to the load drive control signal. The buffer circuit has a pair of gate driven switching elements which are connected to each other in push-pull configuration and driven at their gate terminals by the load drive control signal. The buffer circuit has an output terminal which is connected to a connection point between ends of controlled electrodes of the gate driven switching elements, and a power source terminal and a ground connection terminal respectively connected to the remaining ends of the other controlled electrodes of the gate driven switching elements. A ground connection side element of a pair of gate driven switching elements has a set of MOS transistors which are connected across the connection point and the ground connection terminal.

摘要翻译： 负载驱动装置包括产生负载驱动控制信号的驱动控制信号产生电路和响应于负载驱动控制信号产生输出信号的半导体缓冲电路。 缓冲电路具有一对栅极驱动的开关元件，它们以推挽配置相互连接，并通过负载驱动控制信号在其栅极端子处驱动。 缓冲电路具有连接到栅极驱动的开关元件的受控电极的端部之间的连接点的输出端子，以及分别连接到栅极的其他受控电极的剩余端的电源端子和接地连接端子 驱动开关元件。 一对栅极驱动的开关元件的接地连接侧元件具有连接在连接点和接地连接端子上的一组MOS晶体管。

公开(公告)号：US07671415B2

公开(公告)日：2010-03-02

申请号：US11276823

申请日：2006-03-15

申请人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

发明人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

IPC分类号： H01L23/62

CPC分类号： H01L27/0262

摘要： An electro-static discharge protection circuit and a semiconductor device having the same is disclosed. The electro-static discharge protection circuit has a current control circuit. The current control circuit has a first capacitive element. When the external source voltage is applied to the external source voltage supply line, the booster circuit in the internal circuitry boosts the internal source voltage of the internal source voltage supply line. The external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage. The first capacitive element restricts a current from flowing from the second terminal of the thyristor rectifier circuit to the internal source voltage, even when the external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage. This prevents the thyristor rectifier circuit from malfunctioning and turning on.

摘要翻译： 公开了一种静电放电保护电路及具有该静电放电保护电路的半导体器件。 静电放电保护电路具有电流控制电路。 电流控制电路具有第一电容元件。 当外部电源电压施加到外部电源电源线时，内部电路中的升压电路会提升内部电源电压源的内部源电压。 当升压电路根据外部电源电压提升内部源电压时，外部源电压在升压阶段的早期阶段瞬间大于内部源电压。 第一电容元件限制电流从晶闸管整流电路的第二端子流到内部源极电压，即使在升压电路的早期阶段，当外部电源电压瞬时地大于升压阶段的内部源极电压时， 根据外部源电压提升内部源电压。 这样可以防止晶闸管整流电路发生故障并导通。

公开(公告)号：US20070052033A1

公开(公告)日：2007-03-08

申请号：US11516752

申请日：2006-09-07

申请人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

发明人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L27/0288 ,  Y10T436/206664

摘要： A load driving device includes a drive control signal generation circuit generating a load drive control signal and a semiconductor buffer circuit generating an output signal in response to the load drive control signal. The buffer circuit has a pair of gate driven switching elements which are connected to each other in push-pull configuration and driven at their gate terminals by the load drive control signal. The buffer circuit has an output terminal which is connected to a connection point between ends of controlled electrodes of the gate driven switching elements, and a power source terminal and a ground connection terminal respectively connected to the remaining ends of the other controlled electrodes of the gate driven switching elements. A ground connection side element of a pair of gate driven switching elements has a set of MOS transistors which are connected across the connection point and the ground connection terminal.

摘要翻译： 负载驱动装置包括产生负载驱动控制信号的驱动控制信号产生电路和响应于负载驱动控制信号产生输出信号的半导体缓冲电路。 缓冲电路具有一对栅极驱动的开关元件，它们以推挽配置相互连接，并通过负载驱动控制信号在其栅极端子处驱动。 缓冲电路具有连接到栅极驱动的开关元件的受控电极的端部之间的连接点的输出端子，以及分别连接到栅极的其他受控电极的剩余端的电源端子和接地连接端子 驱动开关元件。 一对栅极驱动的开关元件的接地连接侧元件具有连接在连接点和接地连接端子上的一组MOS晶体管。

公开(公告)号：US07238991B2

公开(公告)日：2007-07-03

申请号：US10947329

申请日：2004-09-23

申请人： Toshikazu Kuroda ,  Katsuhito Sasaki

发明人： Toshikazu Kuroda ,  Katsuhito Sasaki

IPC分类号： H01L23/62

CPC分类号： H01L23/5286 ,  H01L23/585 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/41725 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.

摘要翻译： 同心多边形金属氧化物半导体场效应晶体管被设计为避免中心漏极扩散的角和周围环形栅电极的内角之间的重叠。 例如，可以通过消除角部来减小栅电极来分离直线段。 或者，漏极扩散可以具有十字形状，并且外部环形源极扩散可以被减小到面向十字的端部的直线段，或者源极和漏极扩散和栅电极可以全部被减小以分离直线段。 通过避免角区域的电场集中，这些设计提供了增强的防静电放电保护。

公开(公告)号：US06798022B1

公开(公告)日：2004-09-28

申请号：US10384714

申请日：2003-03-11

申请人： Toshikazu Kuroda ,  Katsuhito Sasaki

发明人： Toshikazu Kuroda ,  Katsuhito Sasaki

IPC分类号： H01L2362

CPC分类号： H01L23/5286 ,  H01L23/585 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/41725 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A concentric polygonal metal-oxide-semiconductor field-effect transistor is designed to avoid overlap between corners of the central drain diffusion and inner corners of the surrounding annular gate electrode. For example, the gate electrode may be reduced to separate straight segments by eliminating the corner portions. Alternatively, the drain diffusion may have a cross shape, and the outer annular source diffusion may be reduced to straight segments facing the ends of the cross, or the source and drain diffusions and gate electrodes may all be reduced to separate straight segments. By avoiding electric field concentration in the corner regions, these designs provide enhanced protection from electrostatic discharge.

摘要翻译： 同心多边形金属氧化物半导体场效应晶体管被设计为避免中心漏极扩散的角和周围环形栅电极的内角之间的重叠。 例如，可以通过消除角部来减小栅电极来分离直线段。 或者，漏极扩散可以具有十字形状，并且外部环形源极扩散可以被减小到面向十字的端部的直线段，或者源极和漏极扩散和栅电极可以全部被减小以分离直线段。 通过避免角区域的电场集中，这些设计提供了增强的防静电放电保护。

公开(公告)号：US5128280A

公开(公告)日：1992-07-07

申请号：US732602

申请日：1991-07-19

申请人： Ryoichi Matsumoto ,  Toshikazu Kuroda ,  Takao Kato

发明人： Ryoichi Matsumoto ,  Toshikazu Kuroda ,  Takao Kato

IPC分类号： G03F9/00 ,  H01L23/544

CPC分类号： G03F9/70 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10S148/05 ,  Y10S148/102 ,  Y10S438/975

摘要： A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si.sub.3 N.sub.4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges. The process can be used to form wafer alignment marks having arbitrary patterns and can be adopted to improve the reliability of automatic alignment without the need to make new masks.

摘要翻译： 晶片制造工艺使用外围蚀刻在晶片衬底周围形成用于掺杂剂扩散和对准标记形成的窗口周边的凹槽，并且在沟槽中形成Si 3 N 4锥形。 虽然最终被去除，但是凹槽产生了在衬底中具有几乎垂直侧壁的图案，当转移到外延层时，其形成具有尖锐边缘的晶片对准标记。 该方法可以用于形成具有任意图案的晶片对准标记，并且可以用于提高自动对准的可靠性，而不需要制作新的掩模。

公开(公告)号：US5106432A

公开(公告)日：1992-04-21

申请号：US523489

申请日：1990-05-15

申请人： Ryoichi Matsumoto ,  Toshikazu Kuroda ,  Takao Kato

发明人： Ryoichi Matsumoto ,  Toshikazu Kuroda ,  Takao Kato

IPC分类号： G03F9/00 ,  H01L23/544

CPC分类号： G03F9/70 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10S148/05 ,  Y10S148/102 ,  Y10S438/975

摘要： A wafer alignment mark consists of patterns, such as a chevron and two stripes, formed in the surface of a semiconductor wafer. Each pattern is defined by a pair of parallel grooves, separation between all pairs of grooves being the same. Each groove provides one sharp edge which can be reliably detected by an automatic alignment system.A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si.sub.3 N.sub.4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges.

摘要翻译： 晶片对准标记由形成在半导体晶片的表面中的图案（例如人字纹和两条）组成。 每个图案由一对平行的凹槽限定，所有成对的凹槽之间的间隔相同。 每个槽提供一个锋利的边缘，可以通过自动对准系统可靠地检测。 晶片制造工艺使用外围蚀刻在晶片衬底周围形成用于掺杂剂扩散和对准标记形成的窗口周边的凹槽，并且在沟槽中形成Si 3 N 4锥形。 虽然最终被去除，但是凹槽产生了在衬底中具有几乎垂直侧壁的图案，当转移到外延层时，其形成具有尖锐边缘的晶片对准标记。