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US5128280A Fabrication process for wafer alignment marks by using peripheral etching to form grooves 失效
通过使用周边蚀刻来形成槽的晶片对准标记的制造工艺

Fabrication process for wafer alignment marks by using peripheral
etching to form grooves
摘要:
A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si.sub.3 N.sub.4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges. The process can be used to form wafer alignment marks having arbitrary patterns and can be adopted to improve the reliability of automatic alignment without the need to make new masks.
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