发明授权
US5128280A Fabrication process for wafer alignment marks by using peripheral
etching to form grooves
失效
通过使用周边蚀刻来形成槽的晶片对准标记的制造工艺
- 专利标题: Fabrication process for wafer alignment marks by using peripheral etching to form grooves
- 专利标题(中): 通过使用周边蚀刻来形成槽的晶片对准标记的制造工艺
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申请号: US732602申请日: 1991-07-19
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公开(公告)号: US5128280A公开(公告)日: 1992-07-07
- 发明人: Ryoichi Matsumoto , Toshikazu Kuroda , Takao Kato
- 申请人: Ryoichi Matsumoto , Toshikazu Kuroda , Takao Kato
- 申请人地址: JPX Tokyo
- 专利权人: Oki Electric Industry Co., Ltd.
- 当前专利权人: Oki Electric Industry Co., Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX1-120532 19890516; JPX1-124393 19890519
- 主分类号: G03F9/00
- IPC分类号: G03F9/00 ; H01L23/544
摘要:
A wafer fabrication process uses peripheral etching to form grooves in a wafer substrate around the periphery of windows opened for dopant diffusion and alignment mark formation, and forms Si.sub.3 N.sub.4 tapers in the grooves. Although ultimately removed, the grooves create a pattern with nearly vertical sidewalls in the substrate which, when transferred to an epitaxial layer, forms wafer alignment marks with sharp edges. The process can be used to form wafer alignment marks having arbitrary patterns and can be adopted to improve the reliability of automatic alignment without the need to make new masks.
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