公开(公告)号：US20110068009A1

公开(公告)日：2011-03-24

申请号：US12991500

申请日：2009-05-20

申请人： Eisaku Okada ,  Hirokazu Hayashi ,  Minoru Hanatani

发明人： Eisaku Okada ,  Hirokazu Hayashi ,  Minoru Hanatani

IPC分类号： B32B15/092 ,  C25D5/00

CPC分类号： C09D5/4438 ,  C08K3/11 ,  C09D5/08 ,  C09D5/4492 ,  C09D7/61 ,  C25D13/02 ,  C25D13/04 ,  C25D13/18 ,  C25D15/02

摘要： This invention concerns a method for forming a coating film on a metallic substrate by a multistage energization method at no less than two stages using an electrodeposition bath which comprises a water-based film-forming agent comprising zirconium compound and, as the base resin, an amino group-containing modified epoxy resin which is obtained through reaction of an epoxy resin with an amino group-containing compound, said epoxy resin having been obtained through reaction of a diepoxide compound, a bisphenol epoxy resin and bisphenols; whereby coated articles excelling in corrosion resistance are offered.

摘要翻译： 本发明涉及一种使用电沉积浴，通过多层通电方法，在不少于两个阶段的金属基底上形成涂膜的方法，所述电沉积浴包含含锆化合物的水性成膜剂，作为基础树脂， 通过环氧树脂与含氨基化合物的反应获得的含氨基的改性环氧树脂，所述环氧树脂通过二环氧化合物，双酚环氧树脂和双酚的反应获得; 从而提供了耐腐蚀性优异的涂层制品。

公开(公告)号：US07723794B2

公开(公告)日：2010-05-25

申请号：US11516752

申请日：2006-09-07

申请人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

发明人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L27/0288 ,  Y10T436/206664

摘要： A load driving device includes a drive control signal generation circuit generating a load drive control signal and a semiconductor buffer circuit generating an output signal in response to the load drive control signal. The buffer circuit has a pair of gate driven switching elements which are connected to each other in push-pull configuration and driven at their gate terminals by the load drive control signal. The buffer circuit has an output terminal which is connected to a connection point between ends of controlled electrodes of the gate driven switching elements, and a power source terminal and a ground connection terminal respectively connected to the remaining ends of the other controlled electrodes of the gate driven switching elements. A ground connection side element of a pair of gate driven switching elements has a set of MOS transistors which are connected across the connection point and the ground connection terminal.

摘要翻译： 负载驱动装置包括产生负载驱动控制信号的驱动控制信号产生电路和响应于负载驱动控制信号产生输出信号的半导体缓冲电路。 缓冲电路具有一对栅极驱动的开关元件，它们以推挽配置相互连接，并通过负载驱动控制信号在其栅极端子处驱动。 缓冲电路具有连接到栅极驱动的开关元件的受控电极的端部之间的连接点的输出端子，以及分别连接到栅极的其他受控电极的剩余端的电源端子和接地连接端子 驱动开关元件。 一对栅极驱动的开关元件的接地连接侧元件具有连接在连接点和接地连接端子上的一组MOS晶体管。

公开(公告)号：US07671415B2

公开(公告)日：2010-03-02

申请号：US11276823

申请日：2006-03-15

申请人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

发明人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

IPC分类号： H01L23/62

CPC分类号： H01L27/0262

摘要： An electro-static discharge protection circuit and a semiconductor device having the same is disclosed. The electro-static discharge protection circuit has a current control circuit. The current control circuit has a first capacitive element. When the external source voltage is applied to the external source voltage supply line, the booster circuit in the internal circuitry boosts the internal source voltage of the internal source voltage supply line. The external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage. The first capacitive element restricts a current from flowing from the second terminal of the thyristor rectifier circuit to the internal source voltage, even when the external source voltage becomes transiently greater than the internal source voltage at the early stage of the boosting step when the booster circuit boosts the internal source voltage based on the external source voltage. This prevents the thyristor rectifier circuit from malfunctioning and turning on.

摘要翻译： 公开了一种静电放电保护电路及具有该静电放电保护电路的半导体器件。 静电放电保护电路具有电流控制电路。 电流控制电路具有第一电容元件。 当外部电源电压施加到外部电源电源线时，内部电路中的升压电路会提升内部电源电压源的内部源电压。 当升压电路根据外部电源电压提升内部源电压时，外部源电压在升压阶段的早期阶段瞬间大于内部源电压。 第一电容元件限制电流从晶闸管整流电路的第二端子流到内部源极电压，即使在升压电路的早期阶段，当外部电源电压瞬时地大于升压阶段的内部源极电压时， 根据外部源电压提升内部源电压。 这样可以防止晶闸管整流电路发生故障并导通。

公开(公告)号：US20080225450A1

公开(公告)日：2008-09-18

申请号：US12073194

申请日：2008-03-03

申请人： Hirokazu Hayashi

发明人： Hirokazu Hayashi

IPC分类号： H02H9/00

CPC分类号： H01L27/0266 ,  H01L27/1203

摘要： A semiconductor integrated circuit having an ESD protection circuit enhancing a durability against thermal destruction is provided. The semiconductor integrated circuit configured by a plurality of MOSFETs each having an SOI structure formed on a silicon substrate includes a functional circuit having an external connection signal terminal, a pair of power terminals and at least one of the MOSFETs. The semiconductor integrated circuit also includes at least one ESD protection circuit having a first terminal and a second terminal connected to the signal terminal and the power terminals, respectively. The ESD protection circuit includes at least one first MOSFET of the MOSFETs formed on the silicon substrate. The first MOSFET has a drain connected to the first terminal, a gate connected to the second terminal, and a source connected to the second terminal. The at least one ESD protection circuit also includes at least one second MOSFET of the MOSFETs formed adjacent to the first MOSFET on the silicon substrate. The second MOSFET has a gate connected to the first terminal and the same conductivity type as the first MOSFET.

摘要翻译： 提供了具有提高耐热破坏耐久性的ESD保护电路的半导体集成电路。 由在硅衬底上形成有SOI结构的多个MOSFET构成的半导体集成电路包括具有外部连接信号端子，一对电源端子和至少一个MOSFET的功能电路。 半导体集成电路还包括至少一个ESD保护电路，其具有分别连接到信号端子和电源端子的第一端子和第二端子。 ESD保护电路包括形成在硅衬底上的MOSFET的至少一个第一MOSFET。 第一MOSFET具有连接到第一端子的漏极，连接到第二端子的栅极和连接到第二端子的源极。 所述至少一个ESD保护电路还包括与所述硅衬底上的所述第一MOSFET相邻形成的所述MOSFET的至少一个第二MOSFET。 第二MOSFET具有连接到第一端子的栅极和与第一MOSFET相同的导电类型。

公开(公告)号：US07302378B2

公开(公告)日：2007-11-27

申请号：US10933271

申请日：2004-09-03

申请人： Hirokazu Hayashi

发明人： Hirokazu Hayashi

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An ESD protection device modeling method of modeling an electrical characteristic of an electrostatic discharge (ESD) protection device for simulating a circuit that include the ESD protection device, comprising the steps of (114) setting a parameter of at least one specific element that affects the electrical characteristic of the ESD protection device; and (116) modeling the electrical characteristic of the ESD protection device with the parameter of the specific element.

摘要翻译： 一种用于对用于模拟包括ESD保护装置的电路的静电放电（ESD）保护装置的电特性建模的ESD保护装置建模方法，包括以下步骤：（114）设置影响所述ESD保护装置的至少一个特定元件的参数 ESD保护装置的电气特性; 和（116）利用特定元件的参数建模ESD保护装置的电气特性。

公开(公告)号：US20070052033A1

公开(公告)日：2007-03-08

申请号：US11516752

申请日：2006-09-07

申请人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

发明人： Toshikazu Kuroda ,  Hirokazu Hayashi ,  Yasuhiro Fukuda

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L27/0288 ,  Y10T436/206664

摘要： A load driving device includes a drive control signal generation circuit generating a load drive control signal and a semiconductor buffer circuit generating an output signal in response to the load drive control signal. The buffer circuit has a pair of gate driven switching elements which are connected to each other in push-pull configuration and driven at their gate terminals by the load drive control signal. The buffer circuit has an output terminal which is connected to a connection point between ends of controlled electrodes of the gate driven switching elements, and a power source terminal and a ground connection terminal respectively connected to the remaining ends of the other controlled electrodes of the gate driven switching elements. A ground connection side element of a pair of gate driven switching elements has a set of MOS transistors which are connected across the connection point and the ground connection terminal.

摘要翻译： 负载驱动装置包括产生负载驱动控制信号的驱动控制信号产生电路和响应于负载驱动控制信号产生输出信号的半导体缓冲电路。 缓冲电路具有一对栅极驱动的开关元件，它们以推挽配置相互连接，并通过负载驱动控制信号在其栅极端子处驱动。 缓冲电路具有连接到栅极驱动的开关元件的受控电极的端部之间的连接点的输出端子，以及分别连接到栅极的其他受控电极的剩余端的电源端子和接地连接端子 驱动开关元件。 一对栅极驱动的开关元件的接地连接侧元件具有连接在连接点和接地连接端子上的一组MOS晶体管。

公开(公告)号：US5452019A

公开(公告)日：1995-09-19

申请号：US140552

申请日：1993-10-25

申请人： Hidenori Fukuda ,  Hirokazu Hayashi

发明人： Hidenori Fukuda ,  Hirokazu Hayashi

IPC分类号： G02F1/133 ,  G09G3/36 ,  H04N9/31 ,  H04N17/02 ,  H04N9/73 ,  H04N3/23

CPC分类号： H04N9/3182 ,  H04N17/02

摘要： A chromaticity meter measures chromaticity of light output for each of picture elements selected. Calculated from the measurement is corrective data on each of RGB colors, which in turn used to calculate corrective data on each of RGB at unselected picture elements. In this method, original video signals for each of RGB colors will be correctively modulated based on the thus obtained corrective data. A projected image displaying apparatus is constructed such that adjustment of chromaticity as to white as well as to black from the measurement by the chromaticity meter of chromaticity throughout the entire image, is carried out uniformly and reliably by automatic control using a microcomputer so as to determine optimal condition for correctively modulating the original video signal. This apparatus further includes means for storing the thus obtained optimal condition in a non-volatile memory.

摘要翻译： 色度计测量所选择的每个图像元素的光输出的色度。 从测量中计算出的每个RGB颜色的校正数据，这些数据又用于计算未选择的图像元素的每个RGB上的校正数据。 在这种方法中，基于由此获得的校正数据将对每种RGB颜色的原始视频信号进行校正调制。 投影图像显示装置被构造成使得通过使用微型计算机的自动控制，通过整个图像将色度的色度调整到通过色度的色度计测量的白色和黑色的色度被均匀可靠地进行，以便确定 对原始视频信号进行正确调制的最佳条件。 该装置还包括用于将如此获得的最佳条件存储在非易失性存储器中的装置。

公开(公告)号：US5089101A

公开(公告)日：1992-02-18

申请号：US701632

申请日：1991-05-15

申请人： Hirokazu Hayashi ,  Tetsuo Aihara ,  Haruo Nagaoka ,  Koji Kamikado ,  Eisaku Nakatani

发明人： Hirokazu Hayashi ,  Tetsuo Aihara ,  Haruo Nagaoka ,  Koji Kamikado ,  Eisaku Nakatani

IPC分类号： C09D5/44 ,  C09D133/04

CPC分类号： C09D5/4473

摘要： A cationic electrodeposition coating composition comprising[A] a neutralization product or a quaternary ammonium salt of a comb-shaped copolymer obtained by copolymerizing (a) 3 to 90 parts by weight of an ethylenically unsaturated monomer having a hydrocarbon chain with at least 8 carbon atoms at the molecular ends, (b) 1 to 50 parts by weight of at least one cationic (meth)acrylic monomer selected from the group consisting of aminoalkyl (meth)acrylates, aminoalkyl (meth)acrylamides (meth)acrylates containing a quaternary ammonium salt group and (meth)acrylamides containing a quaternary ammonium salt group, (c) 1 to 60 parts by weight of an alpha,beta-ethylenically unsaturated monomer other than the monomer (b), and (d) 0 to 95 parts by weight of an alpha,beta-ethylenically unsaturated monomer other than the monomers (a), (b) and (c),[B] a cationic epoxy resin capable of being dissolved or dispersed in water, and[C] a pigment.

摘要翻译： 一种阳离子电沉积涂料组合物，其包含[A]通过使（a）3-90重量份具有至少8个碳原子的烃链的烯键式不饱和单体共聚合的梳状共聚物的中和产物或季铵盐 在分子末端，（b）1至50重量份的至少一种选自（甲基）丙烯酸氨基烷基酯，含有季铵盐的氨基烷基（甲基）丙烯酰胺（甲基）丙烯酸酯）的阳离子（甲基）丙烯酸单体 基团和含有季铵盐基团的（甲基）丙烯酰胺，（c）1至60重量份的除单体（b）之外的α，β-烯属不饱和单体，和（d）0至95重量份的 单体（a），（b）和（c）以外的α，β-烯键式不饱和单体，[B]能够溶解或分散在水中的阳离子型环氧树脂，和[C]颜料。

公开(公告)号：US07859063B2

公开(公告)日：2010-12-28

申请号：US12336257

申请日：2008-12-16

申请人： Hirokazu Hayashi

发明人： Hirokazu Hayashi

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/78603 ,  H01L29/78618 ,  H01L29/78654

摘要： According to a feature of the present invention, a semiconductor device includes a SOI substrate, including a semiconductor substrate; an insulating layer formed on the semiconductor substrate and a silicon layer formed on the insulating layer. A drain region and a source region are formed in the silicon layer so that the source region is in contact with the insulating layer but the drain region is not in contact with the insulating layer.

摘要翻译： 根据本发明的特征，半导体器件包括：SOI衬底，包括半导体衬底; 形成在半导体衬底上的绝缘层和形成在绝缘层上的硅层。 在硅层中形成漏极区域和源极区域，使得源极区域与绝缘层接触，但是漏极区域不与绝缘层接触。

公开(公告)号：US07521713B2

公开(公告)日：2009-04-21

申请号：US11180681

申请日：2005-07-14

申请人： Hirokazu Hayashi

发明人： Hirokazu Hayashi

IPC分类号： H01L29/10 ,  H01L29/76

CPC分类号： H01L27/0251

摘要： A semiconductor device includes a laminated substrate; a removal portion; a cavity; a first semiconductor element; and a second semiconductor element. In the laminated substrate, a bulk layer, an insulating layer, and a semiconductor layer are laminated in this order from a bottom. The laminated substrate includes a first area, a second area adjacent to the first area, and a third area adjacent to the second area in each of the layers. The semiconductor layer, the insulating layer, and an upper portion of the bulk layer in the first area are removed to form the removal portion. A part of the bulk layer in the second area is removed to form the cavity adjacent to the removal portion. The first semiconductor element is formed in the bulk layer in the removal portion as an ESD protection element. The second semiconductor element is formed partially in the semiconductor layer in the second area.

摘要翻译： 半导体器件包括层叠基板; 去除部分; 一个空腔 第一半导体元件; 和第二半导体元件。 在层叠基板中，从底部依次层叠体层，绝缘层和半导体层。 层叠基板包括第一区域，与第一区域相邻的第二区域和与每个层中的第二区域相邻的第三区域。 去除第一区域中的半导体层，绝缘层和本体层的上部以形成去除部分。 去除第二区域中的体积层的一部分以形成与去除部分相邻的空腔。 第一半导体元件形成在去除部分中的体层中作为ESD保护元件。 第二半导体元件部分地形成在第二区域中的半导体层中。