Projected image displaying apparatus and a method of correcting color
unevenness therein
    1.
    发明授权
    Projected image displaying apparatus and a method of correcting color unevenness therein 失效
    投影图像显示装置及其中的颜色不均匀性的校正方法

    公开(公告)号:US5452019A

    公开(公告)日:1995-09-19

    申请号:US140552

    申请日:1993-10-25

    CPC分类号: H04N9/3182 H04N17/02

    摘要: A chromaticity meter measures chromaticity of light output for each of picture elements selected. Calculated from the measurement is corrective data on each of RGB colors, which in turn used to calculate corrective data on each of RGB at unselected picture elements. In this method, original video signals for each of RGB colors will be correctively modulated based on the thus obtained corrective data. A projected image displaying apparatus is constructed such that adjustment of chromaticity as to white as well as to black from the measurement by the chromaticity meter of chromaticity throughout the entire image, is carried out uniformly and reliably by automatic control using a microcomputer so as to determine optimal condition for correctively modulating the original video signal. This apparatus further includes means for storing the thus obtained optimal condition in a non-volatile memory.

    摘要翻译: 色度计测量所选择的每个图像元素的光输出的色度。 从测量中计算出的每个RGB颜色的校正数据,这些数据又用于计算未选择的图像元素的每个RGB上的校正数据。 在这种方法中,基于由此获得的校正数据将对每种RGB颜色的原始视频信号进行校正调制。 投影图像显示装置被构造成使得通过使用微型计算机的自动控制,通过整个图像将色度的色度调整到通过色度的色度计测量的白色和黑色的色度被均匀可靠地进行,以便确定 对原始视频信号进行正确调制的最佳条件。 该装置还包括用于将如此获得的最佳条件存储在非易失性存储器中的装置。

    Design and simulation methods for electrostatic protection circuits
    2.
    发明授权
    Design and simulation methods for electrostatic protection circuits 失效
    静电保护电路的设计与仿真方法

    公开(公告)号:US07434179B2

    公开(公告)日:2008-10-07

    申请号:US11284138

    申请日:2005-11-22

    申请人: Hirokazu Hayashi

    发明人: Hirokazu Hayashi

    IPC分类号: G06F17/50

    摘要: A physical analysis (S2) of the elements used in an ESD protection circuit is performed; parameters of the elements that have a comparatively large effect on ESD protection characteristics are extracted as key parameters (S4); and a mixed-mode device-circuit simulation of the ESD protection circuit is performed, using the key parameters, to optimize the key parameters (S5). This can shorten the time required for designing an ESD circuit.

    摘要翻译: 执行ESD保护电路中使用的元件的物理分析(S 2) 提取对ESD保护特性影响较大的元件的参数作为关键参数(S 4); 并使用关键参数进行ESD保护电路的混合模式器件电路仿真,优化关键参数(S 5)。 这可以缩短设计ESD电路所需的时间。

    Profile extraction method and profile extraction apparatus
    3.
    发明授权
    Profile extraction method and profile extraction apparatus 失效
    剖面提取方法和剖面提取装置

    公开(公告)号:US06581028B1

    公开(公告)日:2003-06-17

    申请号:US09245860

    申请日:1999-02-08

    申请人: Hirokazu Hayashi

    发明人: Hirokazu Hayashi

    IPC分类号: G06F1750

    CPC分类号: G06F17/5018

    摘要: In a profile extraction method, a long channel profile is first extracted through an initial profile generating stage and a long channel profile extraction stage. In a following two-dimensional profile extraction stage, a two-dimensional channel profile extraction stage and a source/drain profile extraction stage are repeated to extract an optimized two-dimensional channel profile and an optimized source/drain profile. In the two-dimensional channel profile extraction stage, a two-dimensional channel profile is extracted from the gate length dependency of the threshold voltage. In addition, in the source/drain profile extraction stage, a source/drain profile is extracted from the substrate bias voltage dependency of the threshold voltage—gate length characteristics.

    摘要翻译: 在配置文件提取方法中,首先通过初始简档生成阶段和长信道简档提取阶段提取长信道分布。 在随后的二维轮廓提取阶段中,重复二维声道轮廓提取阶段和源/漏曲线提取阶段,以提取优化的二维通道轮廓和优化的源/漏曲线。 在二维信道分布提取阶段,根据阈值电压的栅极长度依赖性提取二维信道分布。 此外,在源极/漏极分布提取阶段,从阈值电压 - 栅极长度特性的衬底偏置电压依赖性提取源极/漏极分布。

    CATIONIC ELECTRODEPOSITION COATING COMPOSITION AND COATED ARTICLE
    5.
    发明申请
    CATIONIC ELECTRODEPOSITION COATING COMPOSITION AND COATED ARTICLE 有权
    阳离子电沉积涂料组合物和涂层制品

    公开(公告)号:US20140042031A1

    公开(公告)日:2014-02-13

    申请号:US14113444

    申请日:2012-04-04

    IPC分类号: C25D9/02

    摘要: The present invention provides a cationic electrodeposition coating composition comprising: a specific amino group-containing modified epoxy resin (A); a blocked polyisocyanate curing agent (B); a water-soluble zirconium compound (C); and sulfamic acid, wherein the water-soluble zirconium compound (C) is present in an amount of 10 to 10,000 ppm, calculated as the mass of the elemental zirconium, relative to the mass of the cationic electrodeposition coating composition.

    摘要翻译: 本发明提供一种阳离子电沉积涂料组合物,其包含:含特定氨基的改性环氧树脂(A); 封端多异氰酸酯固化剂(B); 水溶性锆化合物(C); 和氨基磺酸,其中相对于阳离子电沉积涂料组合物的质量,水溶性锆化合物(C)的存在量以元素锆的质量计算为10至10,000ppm。

    Pile Fabric And Method For Producing The Same
    6.
    发明申请
    Pile Fabric And Method For Producing The Same 审中-公开
    桩织物及其生产方法

    公开(公告)号:US20070215231A1

    公开(公告)日:2007-09-20

    申请号:US11578202

    申请日:2005-04-12

    IPC分类号: D03D27/00

    CPC分类号: D04B21/04 D03D27/00 D06C7/00

    摘要: A pile fabric having a ground structure portion having a knitted or woven structure comprising organic fiber yarns and a cut pile portion comprising cut piles knitted or woven in said ground structure and having a single fiber fineness of 0.1 to 2.0 dtex is woven or knitted, ant then subjected to a thermal treatment to thermally shrink the above-mentioned cut piles to obtain the pile fabric in which the cut pile density of the cut pile portion is in a range of 40,000 to 300,000 dtex/cm2 and the cut pile length of the cut piles is in a range of 0.20 to 2.00 mm. If necessary, said pile fabric is used to obtain a vehicle interior material.

    摘要翻译: 具有编织或编织结构的研磨结构部分的绒头织物包括有机纤维纱线和包括在所述研磨结构中编织或编织并且具有0.1至2.0分特的单纤维细度的切割绒头的切割绒头部分被编织或编织 然后进行热处理以热收缩上述切割桩,以获得绒头织物,其中切割绒头部分的绒毛绒毛密度在40,000至300,000dtex / cm 2的范围内。 切割桩的切割桩长度在0.20〜2.00mm的范围内。 如果需要,所述绒头织物用于获得车辆内部材料。

    Method for modeling semiconductor device process
    7.
    发明授权
    Method for modeling semiconductor device process 失效
    半导体器件工艺建模方法

    公开(公告)号:US07197439B2

    公开(公告)日:2007-03-27

    申请号:US10059176

    申请日:2002-01-31

    申请人: Hirokazu Hayashi

    发明人: Hirokazu Hayashi

    IPC分类号: G06F17/10 G06F17/50

    CPC分类号: G06F17/5018

    摘要: A method for using a computer to calculate a pileup state of an impurity in an interface between an Si layer in which a source and a drain are formed, and an SiO2 layer brought in contact with the Si layer at a high speed, wherein data is first set assuming that the Si layer is constituted of a plurality of cells. Subsequently, the impurity is moved to a pileup position of the interface from each cell, and an amount of impurity piled up in each pileup position of the interface is calculated. In this case, a mass of the impurity moving to the interface from each cell is determined as a function of a distance to each pileup position from each cell, and a distance to a source or a drain closest to the cell.

    摘要翻译: 一种使用计算机计算在其中形成源极和漏极的Si层之间的界面中的杂质的堆积状态的方法和与Si层接触的SiO 2层 其中首先设置数据,假设Si层由多个单元构成。 随后,杂质从每个单元移动到界面的堆积位置,并且计算在界面的每个堆积位置堆积的杂质量。 在这种情况下,从每个单元移动到界面的杂质的质量被确定为从每个单元到每个堆积位置的距离的函数,以及到最靠近单元的源极或漏极的距离。

    Design and simulation methods for electrostatic protection circuits
    8.
    发明申请
    Design and simulation methods for electrostatic protection circuits 失效
    静电保护电路的设计与仿真方法

    公开(公告)号:US20060194382A1

    公开(公告)日:2006-08-31

    申请号:US11284138

    申请日:2005-11-22

    申请人: Hirokazu Hayashi

    发明人: Hirokazu Hayashi

    IPC分类号: H01L21/8234 H01L21/336

    摘要: A physical analysis (S2) of the elements used in an ESD protection circuit is performed; parameters of the elements that have a comparatively large effect on ESD protection characteristics are extracted as key parameters (S4); and a mixed-mode device-circuit simulation of the ESD protection circuit is performed, using the key parameters, to optimize the key parameters (S5). This can shorten the time required for designing an ESD circuit.

    摘要翻译: 执行ESD保护电路中使用的元件的物理分析(S 2) 提取对ESD保护特性影响较大的元件的参数作为关键参数(S 4); 并使用关键参数进行ESD保护电路的混合模式器件电路仿真,优化关键参数(S 5)。 这可以缩短设计ESD电路所需的时间。

    METHOD FOR FORMING COATING FILM
    9.
    发明申请
    METHOD FOR FORMING COATING FILM 有权
    形成涂膜的方法

    公开(公告)号:US20110068009A1

    公开(公告)日:2011-03-24

    申请号:US12991500

    申请日:2009-05-20

    IPC分类号: B32B15/092 C25D5/00

    摘要: This invention concerns a method for forming a coating film on a metallic substrate by a multistage energization method at no less than two stages using an electrodeposition bath which comprises a water-based film-forming agent comprising zirconium compound and, as the base resin, an amino group-containing modified epoxy resin which is obtained through reaction of an epoxy resin with an amino group-containing compound, said epoxy resin having been obtained through reaction of a diepoxide compound, a bisphenol epoxy resin and bisphenols; whereby coated articles excelling in corrosion resistance are offered.

    摘要翻译: 本发明涉及一种使用电沉积浴,通过多层通电方法,在不少于两个阶段的金属基底上形成涂膜的方法,所述电沉积浴包含含锆化合物的水性成膜剂,作为基础树脂, 通过环氧树脂与含氨基化合物的反应获得的含氨基的改性环氧树脂,所述环氧树脂通过二环氧化合物,双酚环氧树脂和双酚的反应获得; 从而提供了耐腐蚀性优异的涂层制品。

    Load driving device
    10.
    发明授权
    Load driving device 有权
    负载驱动装置

    公开(公告)号:US07723794B2

    公开(公告)日:2010-05-25

    申请号:US11516752

    申请日:2006-09-07

    IPC分类号: H01L23/62

    摘要: A load driving device includes a drive control signal generation circuit generating a load drive control signal and a semiconductor buffer circuit generating an output signal in response to the load drive control signal. The buffer circuit has a pair of gate driven switching elements which are connected to each other in push-pull configuration and driven at their gate terminals by the load drive control signal. The buffer circuit has an output terminal which is connected to a connection point between ends of controlled electrodes of the gate driven switching elements, and a power source terminal and a ground connection terminal respectively connected to the remaining ends of the other controlled electrodes of the gate driven switching elements. A ground connection side element of a pair of gate driven switching elements has a set of MOS transistors which are connected across the connection point and the ground connection terminal.

    摘要翻译: 负载驱动装置包括产生负载驱动控制信号的驱动控制信号产生电路和响应于负载驱动控制信号产生输出信号的半导体缓冲电路。 缓冲电路具有一对栅极驱动的开关元件,它们以推挽配置相互连接,并通过负载驱动控制信号在其栅极端子处驱动。 缓冲电路具有连接到栅极驱动的开关元件的受控电极的端部之间的连接点的输出端子,以及分别连接到栅极的其他受控电极的剩余端的电源端子和接地连接端子 驱动开关元件。 一对栅极驱动的开关元件的接地连接侧元件具有连接在连接点和接地连接端子上的一组MOS晶体管。