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公开(公告)号:US20190067027A1
公开(公告)日:2019-02-28
申请号:US15801194
申请日:2017-11-01
Inventor: Yin Wang , Hung-Ju Chou , Jiun-Ming Kuo , Wei-Ken Lin , Chun Te Li
IPC: H01L21/3105 , H01L29/78 , H01L29/06 , H01L21/8238
Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further includes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.
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公开(公告)号:US20190305125A1
公开(公告)日:2019-10-03
申请号:US16431352
申请日:2019-06-04
Inventor: Wei-Ken Lin , Chun Te Li , Chih-Peng Hsu
IPC: H01L29/78 , H01L21/321 , H01L21/02 , H01L29/66 , H01L21/8234
Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.
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公开(公告)号:US10964548B2
公开(公告)日:2021-03-30
申请号:US16569815
申请日:2019-09-13
Inventor: Yin Wang , Hung-Ju Chou , Jiun-Ming Kuo , Wei-Ken Lin , Chun Te Li
IPC: H01L21/3105 , H01L29/78 , H01L21/8238 , H01L29/06 , H01L21/02 , H01L29/66 , H01L21/762 , H01L29/08
Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further includes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.
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公开(公告)号:US20200006077A1
公开(公告)日:2020-01-02
申请号:US16569815
申请日:2019-09-13
Inventor: Yin Wang , Hung-Ju Chou , Jiun-Ming Kuo , Wei-Ken Lin , Chun Te Li
IPC: H01L21/3105 , H01L29/78 , H01L21/8238 , H01L29/06
Abstract: A method includes forming a semiconductor capping layer over a first fin in a first region of a substrate, forming a dielectric layer over the semiconductor capping layer, and forming an insulation material over the dielectric layer, an upper surface of the insulation material extending further away from the substrate than an upper surface of the first fin. The method further includes recessing the insulation material to expose a top portion of the first fin, and forming a gate structure over the top portion of the first fin.
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公开(公告)号:US10797175B2
公开(公告)日:2020-10-06
申请号:US16431352
申请日:2019-06-04
Inventor: Wei-Ken Lin , Chun Te Li , Chih-Peng Hsu
IPC: H01L29/78 , H01L29/66 , H01L21/02 , H01L21/321 , H01L21/8234 , H01L27/092 , H01L21/8238
Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.
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公开(公告)号:US10340384B2
公开(公告)日:2019-07-02
申请号:US15967295
申请日:2018-04-30
Inventor: Wei-Ken Lin , Chun Te Li , Chih-Peng Hsu
IPC: H01L29/78 , H01L29/66 , H01L21/02 , H01L21/321 , H01L21/8234
Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.
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公开(公告)号:US20190165156A1
公开(公告)日:2019-05-30
申请号:US15967295
申请日:2018-04-30
Inventor: Wei-Ken Lin , Chun Te Li , Chih-Peng Hsu
IPC: H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/321 , H01L21/02
CPC classification number: H01L29/785 , H01L21/0262 , H01L21/3212 , H01L21/823431 , H01L29/66795
Abstract: A method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the first fin in the PMOS region; and epitaxially growing a first source/drain material over the first fin in the PMOS region, the first source/drain material extending along the top surface and the sidewalls of the first fin in the PMOS region.
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