公开(公告)号：US09245078B2

公开(公告)日：2016-01-26

申请号：US14310444

申请日：2014-06-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Mu-Jen Huang ,  Yu-Sian Jiang ,  Chien-Wen Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5009 ,  G06F17/5081

摘要： A design system for designing an integrated circuit, and the design system includes a processor and a computer readable medium embodying computer program code. The computer program code includes instructions executable by the processor and configured to cause the processor to: modify a circuit design of the integrated circuit to compensate for an impact of layout parameters of the circuit design; generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit; calculate a circuit performance parameter of the integrated circuit using the at least one recommended layout parameter; and generate a layout design of the modified circuit design of the integrated circuit according to the at least one recommended layout parameter.

摘要翻译： 一种用于设计集成电路的设计系统，并且该设计系统包括处理器和体现计算机程序代码的计算机可读介质。 计算机程序代码包括可由处理器执行并被配置为使处理器：修改集成电路的电路设计以补偿电路设计的布局参数的影响的指令; 生成集成电路内的集成电路器件的至少一个推荐布局参数; 使用所述至少一个推荐的布局参数来计算所述集成电路的电路性能参数; 以及根据所述至少一个推荐布局参数生成所述集成电路的修改电路设计的布局设计。

公开(公告)号：US08875076B2

公开(公告)日：2014-10-28

申请号：US14229134

申请日：2014-03-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tang Lin ,  Cheok-Kei Lei ,  Shu-Yu Chen ,  Yu-Ning Chang ,  Hsiao-Hui Chen ,  Chih-Sheng Chang ,  Chien-Wen Chen ,  Clement Hsingjen Wann

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5068 ,  H01L21/823821 ,  H01L27/0207

摘要： A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range.

摘要翻译： 公开了一种用于从具有平面晶体管的器件的第一布局生成具有FinFET的器件的布局的方法和布局生成机。 接收具有多个FinFET有源区域的平面布局，并且生成具有有效面积宽度的对应的FinFET有源区域。 根据有效面积宽度产生心轴，并且被调整为使得每个对应的平面有源区域的每个FinFET有源区域的β数目与β数量的β比率在预定的β比范围内。

公开(公告)号：US20150179550A1

公开(公告)日：2015-06-25

申请号：US14639431

申请日：2015-03-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Kong-Beng Thei ,  Chih-Tsung Yao ,  Heng-Kai Liu ,  Ming-Jer Chiu ,  Chien-Wen Chen

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  G03F1/144 ,  G03F1/36 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

摘要翻译： 提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。 用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。 该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的垂直导电特征图案中的每一个是否违反了设计规则。 如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。 然后形成照相掩模。 可以使用光掩膜形成半导体结构。

公开(公告)号：US09501593B2

公开(公告)日：2016-11-22

申请号：US15065404

申请日：2016-03-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Mu-Jen Huang ,  Chih Chi Hsiao ,  Wei-Ting Lin ,  Tsung-Hsin Yu ,  Chien-Wen Chen ,  Yung-Chow Peng

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： A semiconductor device design method includes generating a layout of a semiconductor device based on schematic data. The layout includes location data for at least one electrical component. The method includes receiving first voltage data associated with at least one electrical component. The method includes receiving second voltage data based on simulation results for the semiconductor device. The method includes incorporating, based on the location data of the at least one electrical component, the first voltage data or the second voltage data in the layout to generate a modified layout. The first voltage data or the second voltage data being incorporated in at least one marker layer of the modified layout. The method includes performing a voltage-dependent design rule check (VDRC) on the modified layout. The VDRC analyzes spacing rules associated with the at least one electrical component based on the first voltage data or the second voltage data.

摘要翻译： 半导体器件设计方法包括基于原理图数据生成半导体器件的布局。 该布局包括用于至少一个电气部件的位置数据。 该方法包括接收与至少一个电气部件相关联的第一电压数据。 该方法包括基于半导体器件的仿真结果接收第二电压数据。 该方法包括基于所述至少一个电气部件的位置数据来结合布局中的第一电压数据或第二电压数据以生成修改的布局。 第一电压数据或第二电压数据被并入修改后的布局的至少一个标记层中。 该方法包括对经修改的布局进行依赖于电压的设计规则检查（VDRC）。 VDRC基于第一电压数据或第二电压数据分析与至少一个电气部件相关联的间隔规则。

公开(公告)号：US09685395B2

公开(公告)日：2017-06-20

申请号：US14639431

申请日：2015-03-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Kong-Beng Thei ,  Chih-Tsung Yao ,  Heng-Kai Liu ,  Ming-Jer Chiu ,  Chien-Wen Chen

IPC分类号： H01L21/00 ,  H01L23/48 ,  G03F1/00 ,  G03F1/36 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L23/481 ,  G03F1/144 ,  G03F1/36 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

公开(公告)号：US09305134B2

公开(公告)日：2016-04-05

申请号：US14540753

申请日：2014-11-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Mu-Jen Huang ,  Chih Chi Hsiao ,  Wei-Ting Lin ,  Tsung-Hsin Yu ,  Chien-Wen Chen ,  Yung-Chow Peng

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： A semiconductor device design method includes extracting voltage data associated with at least one electrical component in a layout of a semiconductor device and based on a result of a simulation of an operation of the semiconductor device. Based on location data of the at least one electrical component, the extracted voltage data is incorporated in the layout to generate a modified layout of the semiconductor device. One or more operations of the method are performed by at least one processor.

摘要翻译： 半导体器件设计方法包括提取与半导体器件的布局中的至少一个电气部件相关联的电压数据，并且基于半导体器件的操作的模拟结果。 基于所述至少一个电气部件的位置数据，将所提取的电压数据并入所述布局中，以生成所述半导体器件的修改的布局。 该方法的一个或多个操作由至少一个处理器执行。