公开(公告)号：US20250149073A1

公开(公告)日：2025-05-08

申请号：US19014455

申请日：2025-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG ,  Yih WANG ,  Fu-An WU

IPC: G11C7/10 ,  G11C5/06 ,  G11C8/08 ,  G11C17/16 ,  G11C17/18 ,  H01L23/522 ,  H01L23/525 ,  H10B20/25

Abstract: A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

公开(公告)号：US20200081636A1

公开(公告)日：2020-03-12

申请号：US16685722

申请日：2019-11-15

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Yu-Hao HSU ,  Cheng Hung LEE ,  Chen-Lin YANG ,  Chiting CHENG ,  Fu-An WU ,  Hung-Jen LIAO ,  Jung-Ping YANG ,  Jonathan Tsung-Yung CHANG ,  Wei Min CHAN ,  Yen-Huei CHEN ,  Yangsyu LIN ,  Chien-Chen LIN

IPC: G06F3/06 ,  H04J14/02 ,  H04B10/27 ,  H04B10/03 ,  G11C16/12 ,  G11C5/14 ,  G11C16/30 ,  G11C11/4074

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.

公开(公告)号：US20210200452A1

公开(公告)日：2021-07-01

申请号：US17201931

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hao HSU ,  Cheng Hung LEE ,  Chen-Lin YANG ,  Chiting CHENG ,  Fu-An WU ,  Hung-Jen LIAO ,  Jung-Ping YANG ,  Jonathan Tsung-Yung CHANG ,  Wei Min CHAN ,  Yen-Huei CHEN ,  Yangsyu LIN ,  Chien-Chen LIN

IPC: G06F3/06 ,  G11C11/4074 ,  G11C16/30 ,  G11C5/14 ,  G11C16/12 ,  H04B10/03 ,  H04B10/27 ,  H04J14/02

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.

公开(公告)号：US20230189512A1

公开(公告)日：2023-06-15

申请号：US18164274

申请日：2023-02-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG ,  Yih WANG ,  Fu-An WU

IPC: H10B20/20 ,  G11C5/06 ,  G11C7/10 ,  G11C8/08 ,  G11C17/18 ,  H01L23/522 ,  H01L23/525 ,  G11C17/16

CPC classification number: H10B20/20 ,  G11C5/063 ,  G11C7/1069 ,  G11C7/1096 ,  G11C8/08 ,  G11C17/18 ,  H01L23/5226 ,  H01L23/5252 ,  G11C17/165

Abstract: A method includes: coupling a first gate to a first word line through a first gate via, wherein the first gate extends along a first direction; coupling the first gate to a second word line through a second gate via, wherein each of the first gate, a second gate, the first gate via and the second gate via is disposed on a first active area which extends along the second direction, wherein the second gate extends along the first direction and is separated from the first gate along a second direction; coupling the first active area to a first bit line through a first conductive via; and aligning the first gate via, the second gate via and the a first conductive via with each other along the second direction.

公开(公告)号：US20230189513A1

公开(公告)日：2023-06-15

申请号：US18164282

申请日：2023-02-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG ,  Yih WANG ,  Fu-An WU

IPC: H10B20/20 ,  G11C7/10 ,  G11C8/08 ,  H01L23/522 ,  G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  G11C5/06

CPC classification number: H10B20/20 ,  G11C7/1096 ,  G11C7/1069 ,  G11C8/08 ,  H01L23/5226 ,  G11C17/165 ,  G11C17/18 ,  H01L23/5252 ,  G11C5/063

Abstract: A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

公开(公告)号：US20220236894A1

公开(公告)日：2022-07-28

申请号：US17717491

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hao HSU ,  Cheng Hung LEE ,  Chen-Lin YANG ,  Chiting CHENG ,  Fu-An WU ,  Hung-Jen LIAO ,  Jung-Ping YANG ,  Jonathan Tsung-Yung CHANG ,  Wei Min CHAN ,  Yen-Huei CHEN ,  Yangsyu LIN ,  Chien-Chen LIN

IPC: G06F3/06 ,  G11C5/14 ,  G11C11/4074 ,  G11C16/12 ,  G11C16/30 ,  H04B10/03 ,  H04B10/27 ,  H04J14/02

Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.

公开(公告)号：US20210183871A1

公开(公告)日：2021-06-17

申请号：US16713967

申请日：2019-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG ,  Yih WANG ,  Fu-An WU

IPC: H01L27/112 ,  G11C7/10 ,  G11C8/08 ,  G11C5/06 ,  G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H01L23/522

Abstract: A structure includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.