公开(公告)号：US11688789B2

公开(公告)日：2023-06-27

申请号：US17198626

申请日：2021-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Liang-Tai Kuo ,  Yu-Chi Chang

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/3115 ,  H01L21/324

CPC classification number: H01L29/513 ,  H01L21/31155 ,  H01L21/324 ,  H01L29/6656 ,  H01L29/66492

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

公开(公告)号：US11063157B1

公开(公告)日：2021-07-13

申请号：US16728452

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Alexander Kalnitsky ,  Shih-Fen Huang ,  Shu-Hui Su ,  Ting-Chen Hsu ,  Tuo-Hsin Chien ,  Felix Ying-Kit Tsui ,  Shi-Min Wu ,  Yu-Chi Chang

IPC: H01L29/94 ,  H01L49/02 ,  H01L23/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/764

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

公开(公告)号：US20200035806A1

公开(公告)日：2020-01-30

申请号：US16117166

申请日：2018-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Liang-Tai Kuo ,  Yu-Chi Chang

IPC: H01L29/51 ,  H01L21/3115 ,  H01L21/324 ,  H01L29/66

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

公开(公告)号：US10529818B1

公开(公告)日：2020-01-07

申请号：US16117166

申请日：2018-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Liang-Tai Kuo ,  Yu-Chi Chang

IPC: H01L21/8234 ,  H01L29/51 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/324

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

公开(公告)号：US20190067138A1

公开(公告)日：2019-02-28

申请号：US15688018

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Shun Lo ,  Ching-Hsien Huang ,  Yu-Chi Chang

IPC: H01L23/13

CPC classification number: H01L23/13 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: A conductive-insulator-semiconductor (CIS) device with low flicker noise is provided. In some embodiments, the CIS device comprises a semiconductor substrate, a pair of source/drain regions, a selectively-conductive channel, and a gate electrode. The pair of source/drain regions is in the semiconductor substrate, and the source/drain regions are laterally spaced. The selectively-conductive channel is in the semiconductor substrate, and extends laterally in a first direction, from one of the source/drain regions to another one of the source/drain regions. The gate electrode comprises a pair of peripheral segments and a central segment. The peripheral segments extend laterally in parallel in the first direction. The central segment covers the selectively-conductive channel and extends laterally in a second direction transverse to the first direction, from one of the peripheral segments to another one of the peripheral segments. A method for manufacturing the CIS device is also provided.

公开(公告)号：US20210202711A1

公开(公告)日：2021-07-01

申请号：US17198626

申请日：2021-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Liang-Tai Kuo ,  Yu-Chi Chang

IPC: H01L29/51 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/324

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.

公开(公告)号：US10692788B2

公开(公告)日：2020-06-23

申请号：US15688018

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Shun Lo ,  Ching-Hsien Huang ,  Yu-Chi Chang

IPC: H01L23/13 ,  H01L21/762 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: A conductive-insulator-semiconductor (CIS) device with low flicker noise is provided. In some embodiments, the CIS device comprises a semiconductor substrate, a pair of source/drain regions, a selectively-conductive channel, and a gate electrode. The pair of source/drain regions is in the semiconductor substrate, and the source/drain regions are laterally spaced. The selectively-conductive channel is in the semiconductor substrate, and extends laterally in a first direction, from one of the source/drain regions to another one of the source/drain regions. The gate electrode comprises a pair of peripheral segments and a central segment. The peripheral segments extend laterally in parallel in the first direction. The central segment covers the selectively-conductive channel and extends laterally in a second direction transverse to the first direction, from one of the peripheral segments to another one of the peripheral segments. A method for manufacturing the CIS device is also provided.

公开(公告)号：US20210202761A1

公开(公告)日：2021-07-01

申请号：US16728452

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Alexander Kalnitsky ,  Shih-Fen Huang ,  Shu-Hui Su ,  Ting-Chen Hsu ,  Tuo-Hsin Chien ,  Felix Ying-Kit Tsui ,  Shi-Min Wu ,  Yu-Chi Chang

IPC: H01L29/94 ,  H01L49/02 ,  H01L23/00 ,  H01L21/764 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

公开(公告)号：US10971596B2

公开(公告)日：2021-04-06

申请号：US16732397

申请日：2020-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Liang-Tai Kuo ,  Yu-Chi Chang

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/3115 ,  H01L21/324

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a source region and a drain region arranged in a semiconductor substrate, where the source region is laterally separated from the drain region. A gate stack is arranged over the semiconductor substrate and between the source region and the drain region. A cap layer is arranged over the gate stack, where a bottom surface of the cap layer contacts a top surface of the gate stack. Sidewall spacers are arranged along sides of the gate stack and the cap layer. A resist protective oxide (RPO) layer is disposed over the cap layer, where the RPO layer extends along sides of the sidewalls spacers to the semiconductor substrate. A contact etch stop layer is arranged over the RPO layer, the source region, and the drain region.