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公开(公告)号:US09679782B1
公开(公告)日:2017-06-13
申请号:US14990526
申请日:2016-01-07
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Yu-Ting Yen , Ying-Ho Chen
IPC: H01L21/3115 , H01L21/3215 , H01L21/02 , H01L21/321 , H01L21/3205 , H01L21/3105
CPC classification number: H01L21/3212 , H01L21/31053 , H01L21/31155 , H01L21/32155 , H01L21/823431 , H01L22/26 , H01L27/0886
Abstract: A planarization method includes at least two steps. One of the steps is to implant at least one impurity into a wafer to form a polish stop layer in the wafer. The other one of the steps is to polish a top surface of the wafer until reaching the polish stop layer.
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公开(公告)号:US10068992B2
公开(公告)日:2018-09-04
申请号:US15590301
申请日:2017-05-09
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Hung Lo , Tzu-Hsiang Hsu , Chia-Jung Hsu , Feng-Cheng Yang , Teng-Chun Tsai , Ying-Ho Chen
IPC: H01L21/82 , H01L29/66 , H01L21/762 , H01L21/8238
Abstract: A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a first protective layer and a second protective layer made of a different material than the first protective layer. The intermediate layer includes a first semiconductor layer disposed over the base layer, the first protective layer covers at least side walls of the first semiconductor layer and the second protective layer covers at least side walls of the first protective layer.
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公开(公告)号:US09337066B2
公开(公告)日:2016-05-10
申请号:US14072210
申请日:2013-11-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yu-Ting Yen , Kao-Feng Liao , Ying-Ho Chen
CPC classification number: H01L21/67057 , B08B3/04 , H01L21/67028 , H01L21/67034 , H01L21/67751 , H01L21/681
Abstract: The present disclosure relates to a wafer cleaning module for post CMP processes that reduces defects (e.g., watermarks, deposited particles) on a substrate, and an associated method. In some embodiments, the wafer cleaning module has a cleaning tank that may receive a semiconductor substrate within a cleaning medium. A pusher is may vertically move the semiconductor substrate from a starting position within the cleaning tank to an ending position. A position sensor may determine a position of the semiconductor substrate relative to a meniscus of the cleaning medium. Based upon the determined position, a control unit is may adjust a location of the starting position to a predetermined distance below the meniscus.
Abstract translation: 本公开内容涉及用于后CMP处理的晶片清洁模块,其减少基板上的缺陷(例如,水印,沉积的颗粒)以及相关联的方法。 在一些实施例中,晶片清洁模块具有可在清洁介质内接收半导体衬底的清洗槽。 推动器可以将半导体衬底从清洗槽内的起始位置垂直移动到结束位置。 位置传感器可以确定半导体衬底相对于清洁介质的弯液面的位置。 基于确定的位置,控制单元可以将起始位置的位置调整到弯月面以下预定距离。
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公开(公告)号:US20150122291A1
公开(公告)日:2015-05-07
申请号:US14072210
申请日:2013-11-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yu-Ting Yen , Kao-Feng Liao , Ying-Ho Chen
CPC classification number: H01L21/67057 , B08B3/04 , H01L21/67028 , H01L21/67034 , H01L21/67751 , H01L21/681
Abstract: The present disclosure relates to a wafer cleaning module for post CMP processes that reduces defects (e.g., watermarks, deposited particles) on a substrate, and an associated method. In some embodiments, the wafer cleaning module has a cleaning tank that may receive a semiconductor substrate within a cleaning medium. A pusher is may vertically move the semiconductor substrate from a starting position within the cleaning tank to an ending position. A position sensor may determine a position of the semiconductor substrate relative to a meniscus of the cleaning medium. Based upon the determined position, a control unit is may adjust a location of the starting position to a predetermined distance below the meniscus.
Abstract translation: 本公开内容涉及用于后CMP处理的晶片清洁模块,其减少基板上的缺陷(例如,水印,沉积的颗粒)以及相关联的方法。 在一些实施例中,晶片清洁模块具有可在清洁介质内接收半导体衬底的清洗槽。 推动器可以将半导体衬底从清洁槽内的起始位置垂直移动到结束位置。 位置传感器可以确定半导体衬底相对于清洁介质的弯液面的位置。 基于确定的位置,控制单元可以将起始位置的位置调整到弯月面以下预定距离。
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