公开(公告)号：US11626482B2

公开(公告)日：2023-04-11

申请号：US17192134

申请日：2021-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Ting Chen ,  Chen-Han Wang ,  Keng-Chu Lin ,  Shuen-Shin Liang ,  Tsu-Hsiu Perng ,  Tsai-Jung Ho ,  Tsung-Han Ko ,  Tetsuji Ueno ,  Yahru Cheng

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/768 ,  H01L29/49

Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.

公开(公告)号：US10573519B2

公开(公告)日：2020-02-25

申请号：US15906187

申请日：2018-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Han Ko ,  Joy Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  H01L21/308 ,  G03F7/20 ,  H01L21/033 ,  H01L21/266 ,  G03F7/038 ,  G03F7/40 ,  G03F7/09 ,  G03F7/039 ,  G03F7/38 ,  G03F7/26

Abstract: A method for performing a photolithography process is provided. The method includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed region and an unexposed region by performing an exposure process. The method includes performing a baking process on the resist layer, so that voids are formed in the exposed region of the resist layer. The method also includes removing the unexposed region of the resist layer to form a recess in the resist layer and filling a post treatment coating material in the recess and the void. The method further includes removing a portion of the post treatment coating material by performing a second develop process, and another portion of the post treatment coating material is left on surfaces of the exposed region of the resist layer to form a patterned resist layer.

公开(公告)号：US12094952B2

公开(公告)日：2024-09-17

申请号：US18297831

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Ting Chen ,  Chen-Han Wang ,  Keng-Chu Lin ,  Shuen-Shin Liang ,  Tsu-Hsiu Perng ,  Tsai-Jung Ho ,  Tsung-Han Ko ,  Tetsuji Ueno ,  Yahru Cheng

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L29/0653 ,  H01L29/6656

Abstract: The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.

公开(公告)号：US10796910B2

公开(公告)日：2020-10-06

申请号：US16731664

申请日：2019-12-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Han Ko ,  Joy Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  G03F7/26 ,  H01L21/033 ,  H01L21/308 ,  H01L21/266 ,  G03F7/038 ,  G03F7/20 ,  G03F7/40 ,  G03F7/09 ,  G03F7/039 ,  G03F7/38

Abstract: A method for performing a photolithography process is provided. The method includes forming a layer over a substrate, and exposing a portion of the layer to form an exposed region. The method also includes performing a baking process on the layer, so that voids are formed in the exposed region of the layer. The method further includes filling the void with a post treatment coating material, and the post treatment coating material is over the exposed region of the layer.