公开(公告)号：US20240251566A1

公开(公告)日：2024-07-25

申请号：US18627334

申请日：2024-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Yen-Chung Ho ,  Pin-Cheng Hsu ,  Han-Ting Tsai ,  Katherine Chiang

IPC: H10B61/00 ,  G06F3/06 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/20 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  H10N50/01 ,  H10N50/80

Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.

公开(公告)号：US20200303456A1

公开(公告)日：2020-09-24

申请号：US16896369

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Min Cao ,  Han-Ting Tsai ,  Pin-Cheng Hsu ,  Yen-Chung Ho

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/02

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The modulating layer is configured to reinforce stability of the free layer by magnetically coupled to the free layer.

公开(公告)号：US20200105830A1

公开(公告)日：2020-04-02

申请号：US16416529

申请日：2019-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Min Cao ,  Han-Ting Tsai ,  Pin-Cheng Hsu ,  Yen-Chung Ho

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.

公开(公告)号：US11049903B2

公开(公告)日：2021-06-29

申请号：US16896369

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Min Cao ,  Han-Ting Tsai ,  Pin-Cheng Hsu ,  Yen-Chung Ho

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/02

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The modulating layer is configured to reinforce stability of the free layer by magnetically coupled to the free layer.

公开(公告)号：US20200006423A1

公开(公告)日：2020-01-02

申请号：US16270484

申请日：2019-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Yen-Chung Ho ,  Pin-Cheng Hsu ,  Han-Ting Tsai ,  Katherine Chiang

IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12 ,  G06F3/06

Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.

公开(公告)号：US11968843B2

公开(公告)日：2024-04-23

申请号：US16270484

申请日：2019-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Yen-Chung Ho ,  Pin-Cheng Hsu ,  Han-Ting Tsai ,  Katherine Chiang

IPC: G06F3/00 ,  G06F3/06 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/20 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  H10N50/01 ,  H10N50/80

Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.

公开(公告)号：US10700125B2

公开(公告)日：2020-06-30

申请号：US16416529

申请日：2019-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Min Cao ,  Han-Ting Tsai ,  Pin-Cheng Hsu ,  Yen-Chung Ho

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/02

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.