公开(公告)号：US20190043878A1

公开(公告)日：2019-02-07

申请号：US16144286

申请日：2018-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Yu Pan ,  Cheng-Bo Shu ,  Chung-Jen Huang ,  Jing-Ru Lin ,  Tsung-Yu Yang ,  Yun-Chi Wu ,  Yueh-Chieh Chu

IPC: H01L27/11568 ,  H01L27/11582 ,  H01L49/02 ,  H01L29/66 ,  H01L29/792 ,  H01L21/311

Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.

公开(公告)号：US20170186762A1

公开(公告)日：2017-06-29

申请号：US15365156

申请日：2016-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Yu Pan ,  Cheng-Bo Shu ,  Chung-Jen Huang ,  Jing-Ru Lin ,  Tsung-Yu Yang ,  Yun-Chi Wu ,  Yueh-Chieh Chu

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/311 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/31111 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.

公开(公告)号：US11532637B2

公开(公告)日：2022-12-20

申请号：US17132258

申请日：2020-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Yu Pan ,  Cheng-Bo Shu ,  Chung-Jen Huang ,  Jing-Ru Lin ,  Tsung-Yu Yang ,  Yun-Chi Wu ,  Yueh-Chieh Chu

IPC: H01L27/11568 ,  H01L27/11582 ,  H01L49/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/792

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

公开(公告)号：US20210111182A1

公开(公告)日：2021-04-15

申请号：US17132258

申请日：2020-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Yu Pan ,  Cheng-Bo Shu ,  Chung-Jen Huang ,  Jing-Ru Lin ,  Tsung-Yu Yang ,  Yun-Chi Wu ,  Yueh-Chieh Chu

IPC: H01L27/11568 ,  H01L21/311 ,  H01L29/792 ,  H01L49/02 ,  H01L29/66 ,  H01L27/11582

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

公开(公告)号：US10269822B2

公开(公告)日：2019-04-23

申请号：US15365156

申请日：2016-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Yu Pan ,  Cheng-Bo Shu ,  Chung-Jen Huang ,  Jing-Ru Lin ,  Tsung-Yu Yang ,  Yun-Chi Wu ,  Yueh-Chieh Chu

IPC: H01L29/792 ,  H01L27/11568 ,  H01L21/311 ,  H01L29/66 ,  H01L27/11582 ,  H01L49/02

Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.

公开(公告)号：US20180138317A1

公开(公告)日：2018-05-17

申请号：US15354098

申请日：2016-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Ru Lin ,  Cheng-Bo Shu ,  Tsung-Yu Yang ,  Chung-Jen Huang

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/6656 ,  H01L29/66833

Abstract: A memory device includes a semiconductor substrate and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-κ metal gate stack disposed on the substrate. The high-κ metal gate stack has a metal gate and a top surface of the control gate is lower than a top surface of the metal gate. The storage layer includes two oxide layers and a nitride layer, and the nitride layer is interposed in between the two oxide layers.

公开(公告)号：US09799755B2

公开(公告)日：2017-10-24

申请号：US15265506

申请日：2016-09-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yu Yang ,  Cheng-Bo Shu ,  Chung-Jen Huang ,  Jing-Ru Lin ,  Jui-Yu Pan ,  Yun-Chi Wu ,  Yueh-Chieh Chu

IPC: H01L29/66 ,  H01L21/33 ,  H01L29/792 ,  H01L21/3115 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/263 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/2633 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/31105 ,  H01L21/31155 ,  H01L21/32 ,  H01L27/11582 ,  H01L28/00

Abstract: A method for manufacturing a memory device includes forming trenches in a substrate to define an active region, filling an insulation material in the trenches, treating at least one portion of the insulation material, removing an upper portion of the insulation material from the trenches, so as to expose upper portions of side surfaces of the active region and to convert remaining portions of the insulation material in the trenches to shallow trench isolation (STI) disposed on opposite sides of the active region, forming a lower oxide layer, a middle charge trapping layer, and an upper oxide layer which cover the exposed upper portions of the side surfaces of the active region, an upper surface of the active region between the side surfaces of the active region, and the STI, and forming a gate layer on the upper oxide layer.