公开(公告)号：US20190043878A1

公开(公告)日：2019-02-07

申请号：US16144286

申请日：2018-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Yu Pan ,  Cheng-Bo Shu ,  Chung-Jen Huang ,  Jing-Ru Lin ,  Tsung-Yu Yang ,  Yun-Chi Wu ,  Yueh-Chieh Chu

IPC: H01L27/11568 ,  H01L27/11582 ,  H01L49/02 ,  H01L29/66 ,  H01L29/792 ,  H01L21/311

Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.

公开(公告)号：US09997527B1

公开(公告)日：2018-06-12

申请号：US15396886

申请日：2017-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Bo Shu ,  Tsung-Yu Yang ,  Chung-Jen Huang

IPC: H01L21/8234 ,  H01L27/11568 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L21/768 ,  H01L21/28 ,  H01L27/11573 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/28185 ,  H01L21/28282 ,  H01L21/76224 ,  H01L21/76895 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833

Abstract: In a method for manufacturing a semiconductor device, a logic well and a high voltage well are respectively formed in second and third regions of a substrate. A first device structure and a second device structure are formed on a first region of the substrate, third and fourth device structures are respectively formed on the logic well and the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed adjacent to the first device structure, between the first device structure and the second device structure, and adjacent to the second device structure. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. First word line and second word lines are respectively formed on the first word line Vt and the second word line Vt.

公开(公告)号：US11532637B2

公开(公告)日：2022-12-20

申请号：US17132258

申请日：2020-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Yu Pan ,  Cheng-Bo Shu ,  Chung-Jen Huang ,  Jing-Ru Lin ,  Tsung-Yu Yang ,  Yun-Chi Wu ,  Yueh-Chieh Chu

IPC: H01L27/11568 ,  H01L27/11582 ,  H01L49/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/792

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

公开(公告)号：US20210111182A1

公开(公告)日：2021-04-15

申请号：US17132258

申请日：2020-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Yu Pan ,  Cheng-Bo Shu ,  Chung-Jen Huang ,  Jing-Ru Lin ,  Tsung-Yu Yang ,  Yun-Chi Wu ,  Yueh-Chieh Chu

IPC: H01L27/11568 ,  H01L21/311 ,  H01L29/792 ,  H01L49/02 ,  H01L29/66 ,  H01L27/11582

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

公开(公告)号：US20190067302A1

公开(公告)日：2019-02-28

申请号：US15935277

申请日：2018-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Chi Wu ,  Cheng-Bo Shu ,  Chien Hung Liu

IPC: H01L27/1157 ,  H01L29/08 ,  H01L29/49 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11573

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

公开(公告)号：US11121047B2

公开(公告)日：2021-09-14

申请号：US16353044

申请日：2019-03-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Bo Shu ,  Tsung-Hua Yang ,  Chung-Jen Huang

IPC: H01L23/58 ,  H01L21/66 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528 ,  H01L21/78

Abstract: A semiconductor structure includes a substrate, a device, a contact via, a metal/dielectric layer, and a test structure. The device is over the substrate. The contact via is connected to the device. The metal/dielectric layer is over the contact via. The metal/dielectric layer includes a first portion and a second portion. The first portion of the metal/dielectric layer has a metallization pattern connected to the contact via. The second portion of the metal/dielectric layer is void of metal. The test structure is over the second portion of the metal/dielectric layer.

公开(公告)号：US10672783B2

公开(公告)日：2020-06-02

申请号：US15935277

申请日：2018-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Chi Wu ,  Cheng-Bo Shu ,  Chien Hung Liu

IPC: H01L29/792 ,  H01L27/1157 ,  H01L29/66 ,  H01L27/11573 ,  H01L29/08 ,  H01L29/49 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

公开(公告)号：US20190393230A1

公开(公告)日：2019-12-26

申请号：US16562850

申请日：2019-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Chi Wu ,  Cheng-Bo Shu ,  Chien Hung Liu

IPC: H01L27/1157 ,  H01L21/28 ,  H01L29/49 ,  H01L29/08 ,  H01L29/792 ,  H01L27/11573 ,  H01L29/66

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

公开(公告)号：US10276728B2

公开(公告)日：2019-04-30

申请号：US15644506

申请日：2017-07-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Bo Shu ,  Yun-Chi Wu ,  Chung-Jen Huang

IPC: H01L29/792 ,  H01L27/1157 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

公开(公告)号：US20180151585A1

公开(公告)日：2018-05-31

申请号：US15396886

申请日：2017-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Bo Shu ,  Tsung-Yu Yang ,  Chung-Jen Huang

IPC: H01L27/11568 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L21/768 ,  H01L21/28 ,  H01L27/11573 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/28185 ,  H01L21/28282 ,  H01L21/76224 ,  H01L21/76895 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833

Abstract: In a method for manufacturing a semiconductor device, a logic well and a high voltage well are respectively formed in second and third regions of a substrate. A first device structure and a second device structure are formed on a first region of the substrate, third and fourth device structures are respectively formed on the logic well and the high voltage well. A first word line Vt, a source side junction, and a second word line Vt are formed adjacent to the first device structure, between the first device structure and the second device structure, and adjacent to the second device structure. The fourth device structure is removed. A source line junction is formed in the source side junction. The third device structure is removed. First word line and second word lines are respectively formed on the first word line Vt and the second word line Vt.