-
公开(公告)号：US11411571B2
公开(公告)日：2022-08-09
申请号：US17330818
申请日：2021-05-26
发明人： Sandeep Kumar Goel , Ji-Jan Chen , Stanley John , Yun-Han Lee , Yen-Hao Huang
摘要： A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
-
公开(公告)号：US10256828B2
公开(公告)日：2019-04-09
申请号：US15711201
申请日：2017-09-21
发明人： Sandeep Kumar Goel , Ji-Jan Chen , Stanley John , Yun-Han Lee , Yen-Hao Huang
摘要： A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
-
公开(公告)号：US10156609B2
公开(公告)日：2018-12-18
申请号：US15602365
申请日：2017-05-23
发明人： Sandeep Kumar Goel , Stanley John , Ji-Jan Chen , Yun-Han Lee
IPC分类号： G01R31/3183 , H03K19/20 , G01R31/28
摘要： A device includes a fault generation circuit and a first fault injection circuit. The fault generation circuit is configured to generate a fault signal and a plurality of control signals according to a mode signal. The first fault injection circuit is configured to inject a first final fault signal to an under-test device based on the fault signal and the plurality of control signals, in order to verify robustness of the under-test device.
-
公开(公告)号：US10680627B2
公开(公告)日：2020-06-09
申请号：US16372706
申请日：2019-04-02
发明人： Sandeep Kumar Goel , Ji-Jan Chen , Stanley John , Yun-Han Lee , Yen-Hao Huang
摘要： A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
-
公开(公告)号：US11025261B2
公开(公告)日：2021-06-01
申请号：US16894607
申请日：2020-06-05
发明人： Sandeep Kumar Goel , Ji-Jan Chen , Stanley John , Yun-Han Lee , Yen-Hao Huang
摘要： A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
-
公开(公告)号：US20190229737A1
公开(公告)日：2019-07-25
申请号：US16372706
申请日：2019-04-02
发明人： Sandeep Kumar GOEL , Ji-Jan Chen , Stanley John , Yun-Han Lee , Yen-Hao Huang
摘要： A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.015 秒)
