公开(公告)号：US20240079356A1

公开(公告)日：2024-03-07

申请号：US18151623

申请日：2023-01-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsien-Wei Chen ,  Chieh-Lung Lai ,  Meng-Liang Lin ,  Chun-Yueh Yang ,  Shin-Puu Jeng

IPC分类号： H01L23/66 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H10B80/00

CPC分类号： H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H10B80/00 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/15174 ,  H01L2924/15311

摘要： An integrated circuit package includes an interposer, the interposer including: a first redistribution layer, a second redistribution layer over the first redistribution layer in a central region of the interposer, a dielectric layer over the first redistribution layer in a periphery of the interposer, the dielectric layer surrounding the second redistribution layer in a top-down view, a third redistribution layer over the second redistribution layer and the dielectric layer, and a first direct via extending through the dielectric layer. A conductive feature of the third redistribution layer is coupled to a conductive feature of the first redistribution layer through the first direct via.