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    High-speed CMOS ring voltage controlled oscillator with low supply sensitivity
    1.
    发明授权
    High-speed CMOS ring voltage controlled oscillator with low supply sensitivity 有权
    具有低电源灵敏度的高速CMOS环形压控振荡器

    公开(公告)号：US09319031B2

    公开(公告)日：2016-04-19

    申请号：US14225079

    申请日：2014-03-25

    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

    Inventor： Michael M. Green ,  Xiaoyan Gui

    IPC: H03K3/03 ,  H03K3/011 ,  H03B5/04 ,  H03B27/00 ,  H03L1/00

    CPC classification number: H03K3/0322 ,  H03B5/04 ,  H03B27/00 ,  H03B2201/038 ,  H03B2202/042 ,  H03K3/011 ,  H03L1/00

    Abstract: High-speed CMOS ring voltage controlled oscillators with low supply sensitivity have been disclosed. According to one embodiment, a CML ring oscillator comprises a CML negative impedance compensation circuit comprising two cross coupled transistors and a resistor connected to the two transistors for resistive biasing and a CML interpolating delay cell connected in parallel with the CML negative impedance compensation. An impedance change of the CML negative impedance compensation due to supply variation counteracts an impedance change of the CML interpolating delay cell.

    Abstract translation: 已经公开了具有低供应灵敏度的高速CMOS环形电压控制振荡器。 根据一个实施例，CML环形振荡器包括CML负阻抗补偿电路，其包括两个交叉耦合晶体管和连接到两个用于电阻偏置的晶体管的电阻器以及与CML负阻抗补偿并联连接的CML内插延迟单元。 由于电源变化引起的CML负阻抗补偿的阻抗变化抵消了CML内插延迟单元的阻抗变化。

    REFERENCELESS CLOCK RECOVERY CIRCUIT WITH WIDE FREQUENCY ACQUISITION RANGE
    2.
    发明申请
    REFERENCELESS CLOCK RECOVERY CIRCUIT WITH WIDE FREQUENCY ACQUISITION RANGE 有权
    具有宽频率采集范围的无参考时钟恢复电路

    公开(公告)号：US20150349945A1

    公开(公告)日：2015-12-03

    申请号：US14716593

    申请日：2015-05-19

    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

    Inventor： Michael M. Green ,  Sui Huang

    IPC: H04L7/033 ,  H04B1/00

    CPC classification number: H04L7/033 ,  H03J2200/10 ,  H03L7/0891 ,  H04B1/0082 ,  H04L7/0004 ,  H04L7/0087 ,  H04L25/00

    Abstract: A full-rate referenceless clock-data recovery architecture with neither a frequency detector nor a lock detector that allows both frequency and phase locking in a single loop. According to one embodiment, a referenceless clock data recovery (CDR) circuit, comprises a digital control circuit (DCC), a phase and strobe point detector circuit (PSPD), and an LC voltage control oscillator (LC VCO) electrically coupled to the PSPD and DCC such that a frequency of the LC VCO decreases when a negative strobe point is detected and an initial frequency of the LC VCO is higher than an input data bit rate.

    Abstract translation: 具有频率检测器和锁定检测器的全速率无参考时钟数据恢复架构，允许在单个回路中进行频率和相位锁定。 根据一个实施例，无参考时钟数据恢复（CDR）电路包括数字控制电路（DCC），相位和选通点检测器电路（PSPD）以及电耦合到PSPD的LC压控振荡器（LC VCO） 和DCC，使得当检测到负选通点并且LC VCO的初始频率高于输入数据比特率时，LC VCO的频率降低。

    HIGH-SPEED CMOS RING VOLTAGE CONTROLLED OSCILLATOR WITH LOW SUPPLY SENSITIVITY
    3.
    发明申请
    HIGH-SPEED CMOS RING VOLTAGE CONTROLLED OSCILLATOR WITH LOW SUPPLY SENSITIVITY 审中-公开
    高速CMOS环电压控制振荡器，具有低供电灵敏度

    公开(公告)号：US20140292420A1

    公开(公告)日：2014-10-02

    申请号：US14225079

    申请日：2014-03-25

    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

    Inventor： Michael M. Green ,  Xiaoyan Gui

    IPC: H03K3/03

    CPC classification number: H03K3/0322 ,  H03B5/04 ,  H03B27/00 ,  H03B2201/038 ,  H03B2202/042 ,  H03K3/011 ,  H03L1/00

    Abstract: High-speed CMOS ring voltage controlled oscillators with low supply sensitivity have been disclosed. According to one embodiment, a CML ring oscillator comprises a CML negative impedance compensation circuit comprising two cross coupled transistors and a resistor connected to the two transistors for resistive biasing and a CML interpolating delay cell connected in parallel with the CML negative impedance compensation. An impedance change of the CML negative impedance compensation due to supply variation counteracts an impedance change of the CML interpolating delay cell.

    Abstract translation: 已经公开了具有低供应灵敏度的高速CMOS环形电压控制振荡器。 根据一个实施例，CML环形振荡器包括CML负阻抗补偿电路，其包括两个交叉耦合晶体管和连接到两个用于电阻偏置的晶体管的电阻器以及与CML负阻抗补偿并联连接的CML内插延迟单元。 由于电源变化引起的CML负阻抗补偿的阻抗变化抵消了CML内插延迟单元的阻抗变化。

    Referenceless clock recovery circuit with wide frequency acquisition range
    4.
    发明授权
    Referenceless clock recovery circuit with wide frequency acquisition range 有权
    无参考时钟恢复电路具有宽频率采集范围

    公开(公告)号：US09525544B2

    公开(公告)日：2016-12-20

    申请号：US14716593

    申请日：2015-05-19

    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

    Inventor： Michael M. Green ,  Sui Huang

    IPC: H03D3/24 ,  H04L7/033 ,  H04B1/00 ,  H04L7/00 ,  H04L25/00 ,  H03L7/089

    CPC classification number: H04L7/033 ,  H03J2200/10 ,  H03L7/0891 ,  H04B1/0082 ,  H04L7/0004 ,  H04L7/0087 ,  H04L25/00

    Abstract: A full-rate referenceless clock-data recovery architecture with neither a frequency detector nor a lock detector that allows both frequency and phase locking in a single loop. According to one embodiment, a referenceless clock data recovery (CDR) circuit, comprises a digital control circuit (DCC), a phase and strobe point detector circuit (PSPD), and an LC voltage control oscillator (LC VCO) electrically coupled to the PSPD and DCC such that a frequency of the LC VCO decreases when a negative strobe point is detected and an initial frequency of the LC VCO is higher than an input data bit rate.

    Abstract translation: 具有频率检测器和锁定检测器的全速率无参考时钟数据恢复架构，允许在单个回路中进行频率和相位锁定。 根据一个实施例，无参考时钟数据恢复（CDR）电路包括数字控制电路（DCC），相位和选通点检测器电路（PSPD）以及电耦合到PSPD的LC压控振荡器（LC VCO） 和DCC，使得当检测到负选通点并且LC VCO的初始频率高于输入数据比特率时，LC VCO的频率降低。

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