公开(公告)号：US09525544B2

公开(公告)日：2016-12-20

申请号：US14716593

申请日：2015-05-19

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Michael M. Green ,  Sui Huang

IPC: H03D3/24 ,  H04L7/033 ,  H04B1/00 ,  H04L7/00 ,  H04L25/00 ,  H03L7/089

CPC classification number: H04L7/033 ,  H03J2200/10 ,  H03L7/0891 ,  H04B1/0082 ,  H04L7/0004 ,  H04L7/0087 ,  H04L25/00

Abstract: A full-rate referenceless clock-data recovery architecture with neither a frequency detector nor a lock detector that allows both frequency and phase locking in a single loop. According to one embodiment, a referenceless clock data recovery (CDR) circuit, comprises a digital control circuit (DCC), a phase and strobe point detector circuit (PSPD), and an LC voltage control oscillator (LC VCO) electrically coupled to the PSPD and DCC such that a frequency of the LC VCO decreases when a negative strobe point is detected and an initial frequency of the LC VCO is higher than an input data bit rate.

Abstract translation: 具有频率检测器和锁定检测器的全速率无参考时钟数据恢复架构，允许在单个回路中进行频率和相位锁定。 根据一个实施例，无参考时钟数据恢复（CDR）电路包括数字控制电路（DCC），相位和选通点检测器电路（PSPD）以及电耦合到PSPD的LC压控振荡器（LC VCO） 和DCC，使得当检测到负选通点并且LC VCO的初始频率高于输入数据比特率时，LC VCO的频率降低。

公开(公告)号：US20150349945A1

公开(公告)日：2015-12-03

申请号：US14716593

申请日：2015-05-19

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： Michael M. Green ,  Sui Huang

IPC: H04L7/033 ,  H04B1/00

CPC classification number: H04L7/033 ,  H03J2200/10 ,  H03L7/0891 ,  H04B1/0082 ,  H04L7/0004 ,  H04L7/0087 ,  H04L25/00

Abstract: A full-rate referenceless clock-data recovery architecture with neither a frequency detector nor a lock detector that allows both frequency and phase locking in a single loop. According to one embodiment, a referenceless clock data recovery (CDR) circuit, comprises a digital control circuit (DCC), a phase and strobe point detector circuit (PSPD), and an LC voltage control oscillator (LC VCO) electrically coupled to the PSPD and DCC such that a frequency of the LC VCO decreases when a negative strobe point is detected and an initial frequency of the LC VCO is higher than an input data bit rate.

Abstract translation: 具有频率检测器和锁定检测器的全速率无参考时钟数据恢复架构，允许在单个回路中进行频率和相位锁定。 根据一个实施例，无参考时钟数据恢复（CDR）电路包括数字控制电路（DCC），相位和选通点检测器电路（PSPD）以及电耦合到PSPD的LC压控振荡器（LC VCO） 和DCC，使得当检测到负选通点并且LC VCO的初始频率高于输入数据比特率时，LC VCO的频率降低。