公开(公告)号：US20240071892A1

公开(公告)日：2024-02-29

申请号：US17900446

申请日：2022-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kwang-Soo KIM ,  Vivek ARORA ,  Woochan KIM

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4825 ,  H01L21/4839 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49861 ,  H01L23/49866 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/48137 ,  H01L2224/48225 ,  H01L2224/48245 ,  H01L2224/48464 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182

Abstract: In examples, a method of manufacturing a semiconductor package comprises providing a lead frame having multiple conductive pins coupled thereto; positioning the lead frame within a mold chase and applying a strip of mold compound to the multiple conductive pins along a length of the lead frame; trimming connections between the lead frame and the multiple conductive pins; bending the multiple conductive pins; trimming the strip of mold compound to singulate the multiple conductive pins from each other and from the lead frame to form singulated conductive pins; coupling a singulated conductive pin from among the singulated conductive pins to a substrate such that a portion of the strip of mold compound coupled to the singulated conductive pin is in contact with the substrate and such that a segment of the singulated conductive pin extends vertically in a plane that is orthogonal to the substrate; coupling a semiconductor die to the substrate; and covering the substrate, the semiconductor die, the portion of the strip of mold compound, and part of the singulated conductive pin with a second mold compound, such that a portion of the segment of the singulated conductive pin extends beyond a top surface of the second mold compound.

公开(公告)号：US20250140624A1

公开(公告)日：2025-05-01

申请号：US18496667

申请日：2023-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hau NGUYEN ,  Vivek ARORA ,  Patrick Francis THOMPSON ,  Masamitsu MATSUURA ,  Daiki KOMATSU

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/29 ,  H01L25/065

Abstract: A wafer chip scale package (WCSP) comprises first and second dies in differing voltage domains and an isolation material between the first and second dies and contacting multiple surfaces of each of the first and second dies. The package also comprises a first resin material contacting multiple surfaces of the isolation material, with the isolation material between the resin material and the first and second dies. The package also comprises a fiberglass material contacting a surface of the resin material and a second resin material contacting a surface of the fiberglass material. The package also comprises first and second conductive structures coupled to the first and second dies, respectively. The package also includes a passivation material contacting the first and second dies and the first and second conductive structures.