Analog-to-digital converter
    1.
    发明授权
    Analog-to-digital converter 有权
    模数转换器

    公开(公告)号:US09240801B2

    公开(公告)日:2016-01-19

    申请号:US14211233

    申请日:2014-03-14

    Abstract: A delta sigma analog-to-digital converter (ADC) providing optimized performance and energy consumption. In one embodiment, a delta-sigma ADC includes a loop filter and a multi-bit quantizer. The multi-bit quantizer is coupled to the loop filter. The quantizer includes a counter, a reference voltage generator, and a comparator. The counter is configured to provide a multi-bit output value that estimates an output of the loop filter. The reference voltage generator is configured to generate a reference voltage ramp based on the output value of the counter. The comparator is coupled to the reference voltage generator to compare the reference voltage ramp to output of the loop filter.

    Abstract translation: 提供优化的性能和能耗的Δ-Σ模数转换器(ADC)。 在一个实施例中,Δ-ΣADC包括环路滤波器和多位量化器。 多位量化器耦合到环路滤波器。 量化器包括计数器,参考电压发生器和比较器。 计数器被配置为提供估计环路滤波器的输出的多位输出值。 参考电压发生器被配置为基于计数器的输出值产生参考电压斜坡。 比较器耦合到参考电压发生器,以将参考电压斜坡与环路滤波器的输出进行比较。

    ANALOG-TO-DIGITAL CONVERTER
    2.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER 有权
    模拟数字转换器

    公开(公告)号:US20150263759A1

    公开(公告)日:2015-09-17

    申请号:US14211233

    申请日:2014-03-14

    Abstract: A delta sigma analog-to-digital converter (ADC) providing optimized performance and energy consumption. In one embodiment, a delta-sigma ADC includes a loop filter and a multi-bit quantizer. The multi-bit quantizer is coupled to the loop filter. The quantizer includes a counter, a reference voltage generator, and a comparator. The counter is configured to provide a multi-bit output value that estimates an output of the loop filter. The reference voltage generator is configured to generate a reference voltage ramp based on the output value of the counter. The comparator is coupled to the reference voltage generator to compare the reference voltage ramp to output of the loop filter.

    Abstract translation: 提供优化的性能和能耗的Δ-Σ模数转换器(ADC)。 在一个实施例中,Δ-ΣADC包括环路滤波器和多位量化器。 多位量化器耦合到环路滤波器。 量化器包括计数器,参考电压发生器和比较器。 计数器被配置为提供估计环路滤波器的输出的多位输出值。 参考电压发生器被配置为基于计数器的输出值产生参考电压斜坡。 比较器耦合到参考电压发生器,以将参考电压斜坡与环路滤波器的输出进行比较。

    DYNAMIC BROWN-OUT THRESHOLD VOLTAGE FOR POWER CONTROL
    4.
    发明申请
    DYNAMIC BROWN-OUT THRESHOLD VOLTAGE FOR POWER CONTROL 有权
    用于功率控制的动态欠压阈值电压

    公开(公告)号:US20160285438A1

    公开(公告)日:2016-09-29

    申请号:US14665843

    申请日:2015-03-23

    CPC classification number: H02M1/36 H03K17/22

    Abstract: A method of operating a power up circuit is disclosed. The method includes receiving an input voltage and creating a plurality of sample voltages from the input voltage. One of the sample voltages is selected and compared to a reference voltage. The power up circuit produces a brown-out signal in response to the step of comparing.

    Abstract translation: 公开了一种操作上电电路的方法。 该方法包括从输入电压接收输入电压并产生多个采样电压。 选择一个采样电压并将其与参考电压进行比较。 上电电路响应于比较步骤产生欠压信号。

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