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17 条记录 (耗时 0.015 秒)

    Low area and high speed termination detection circuit with voltage clamping
    1.
    发明授权
    Low area and high speed termination detection circuit with voltage clamping 有权

    公开(公告)号：US11621711B2

    公开(公告)日：2023-04-04

    申请号：US17374319

    申请日：2021-07-13

    申请人： Texas Instruments Incorporated

    发明人： Anant Shankar Kamath ,  Kanteti Amar ,  Bharath Kumar Singareddy ,  Rakesh Hariharan

    IPC分类号： H03K19/00

    摘要： Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.

    Isolated Universal Serial Bus Repeater with High Speed Capability
    3.
    发明申请
    Isolated Universal Serial Bus Repeater with High Speed Capability 有权

    公开(公告)号：US20220350766A1

    公开(公告)日：2022-11-03

    申请号：US17246137

    申请日：2021-04-30

    申请人： Texas Instruments Incorporated

    发明人： Anant Shankar Kamath ,  Rakesh Hariharan ,  Mark Edward Wentroble

    IPC分类号： G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  H03K5/24

    摘要： An isolating repeater and corresponding method for Universal Serial Bus (USB) communications. The isolating repeater includes, on either side of a galvanic isolation barrier, front end circuitry coupled to a pair of external terminals, a full speed (FS) transceiver adapted to drive and receive signals over one or more FS isolation channels, and a high speed (HS) transceiver adapted to drive signals over a one HS isolation channel and receive signals over another HS isolation channel. The front end circuitry encodes received signals corresponding to HS data into two-state signals for transmission over one HS isolation channel, and encodes received signals corresponding to HS signaling into two-state signals for transmission over one or more of the FS isolation channels. The front end circuitry on the other side of the isolation barrier decodes the two-state signals received over the one or more FS isolation channels and the two-state signals received over the HS isolation channel for transmission at its external terminals.

    LOW AREA AND HIGH SPEED TERMINATION DETECTION CIRCUIT WITH VOLTAGE CLAMPING
    5.
    发明申请
    LOW AREA AND HIGH SPEED TERMINATION DETECTION CIRCUIT WITH VOLTAGE CLAMPING 有权

    公开(公告)号：US20230022405A1

    公开(公告)日：2023-01-26

    申请号：US17374319

    申请日：2021-07-13

    申请人： Texas Instruments Incorporated

    发明人： Anant Shankar Kamath ,  Kanteti Amar ,  Bharath Kumar Singareddy ,  Rakesh Hariharan

    IPC分类号： H03K19/00

    摘要： Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.

    ON-CHIP CURRENT SENSOR
    6.
    发明申请
    ON-CHIP CURRENT SENSOR 有权

    公开(公告)号：US20210208197A1

    公开(公告)日：2021-07-08

    申请号：US17139246

    申请日：2020-12-31

    申请人： Texas Instruments Incorporated

    发明人： Guha Lakshmanan ,  Rakesh Hariharan ,  Lakshmanan Balasubramanian

    IPC分类号： G01R31/317 ,  G01R3/00

    摘要： A packaged electronic device has a die with a load circuit, a resistor and an analog to digital converter (ADC). The resistor is coupled between a supply node of the die and a power input of the load circuit. The ADC has a first input coupled to a first terminal of the resistor, and a second input coupled to a second terminal of the resistor to measure a voltage across the resistor while a supply voltage is applied to the supply node to determine a load current conducted by the load circuit. A method of manufacturing a packaged electronic device includes wafer processing to fabricate the load circuit, the resistor and the ADC on or in a die area of the wafer with the resistor coupled between the power input of the load circuit and the supply node of the die area.

    Stackable timer
    9.
    发明授权
    Stackable timer 有权

    公开(公告)号：US11133804B1

    公开(公告)日：2021-09-28

    申请号：US17127167

    申请日：2020-12-18

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Rakesh Hariharan ,  Sumantha Manoor Madhyastha

    IPC分类号： H03K19/177 ,  G06F1/08 ,  H03K21/08 ,  G06F115/02

    摘要： An system-on-a-chip (“SoC”) is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block.