公开(公告)号：US11621711B2

公开(公告)日：2023-04-04

申请号：US17374319

申请日：2021-07-13

Applicant: Texas Instruments Incorporated

Inventor： Anant Shankar Kamath ,  Kanteti Amar ,  Bharath Kumar Singareddy ,  Rakesh Hariharan

IPC: H03K19/00

Abstract: Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.

公开(公告)号：US20230025757A1

公开(公告)日：2023-01-26

申请号：US17489483

申请日：2021-09-29

Applicant: Texas Instruments Incorporated

Inventor： RR Manikandan ,  Kumar Anurag Shrivastava ,  Robert Floyd Payne ,  Anant Shankar Kamath ,  Swaminathan Sankaran ,  Kishalay Datta ,  Siraj Akhtar ,  Mark Edward Wentroble ,  Suvadip Banerjee ,  Rakesh Hariharan ,  Gurumurti Kailaschandra Avhad

IPC: H04B1/44 ,  H03K3/017 ,  H03K5/24 ,  H04L27/04 ,  H04L27/06

Abstract: In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.

公开(公告)号：US20220350766A1

公开(公告)日：2022-11-03

申请号：US17246137

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Anant Shankar Kamath ,  Rakesh Hariharan ,  Mark Edward Wentroble

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  H03K5/24

Abstract: An isolating repeater and corresponding method for Universal Serial Bus (USB) communications. The isolating repeater includes, on either side of a galvanic isolation barrier, front end circuitry coupled to a pair of external terminals, a full speed (FS) transceiver adapted to drive and receive signals over one or more FS isolation channels, and a high speed (HS) transceiver adapted to drive signals over a one HS isolation channel and receive signals over another HS isolation channel. The front end circuitry encodes received signals corresponding to HS data into two-state signals for transmission over one HS isolation channel, and encodes received signals corresponding to HS signaling into two-state signals for transmission over one or more of the FS isolation channels. The front end circuitry on the other side of the isolation barrier decodes the two-state signals received over the one or more FS isolation channels and the two-state signals received over the HS isolation channel for transmission at its external terminals.

公开(公告)号：US20230065119A1

公开(公告)日：2023-03-02

申请号：US17709812

申请日：2022-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark E. Wentroble ,  Suzanne M. Vining ,  Rakesh Hariharan ,  Anant Kamath ,  Prajwala Puttappa

IPC: G06F13/38 ,  G06F13/42 ,  G06F9/4401

Abstract: Various configurations of high-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral, and methods of operating the same, are provided to improve the Remote Wake sequence. Repeaters include circuitry to detect the start of Resume signaling or the end of Resume, following initiation of Remote Wake. In an example, pull-up resistors coupled to upstream differential signal lines and a detection circuit with a current source are controlled to detect the start of Resume signaling. In another example, the upstream-side pull-resistors and an enable signal to an upstream-side transmitter are controlled to detect the end of Resume.

公开(公告)号：US20230022405A1

公开(公告)日：2023-01-26

申请号：US17374319

申请日：2021-07-13

Applicant: Texas Instruments Incorporated

Inventor： Anant Shankar Kamath ,  Kanteti Amar ,  Bharath Kumar Singareddy ,  Rakesh Hariharan

IPC: H03K19/00

Abstract: Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.

公开(公告)号：US20210208197A1

公开(公告)日：2021-07-08

申请号：US17139246

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Guha Lakshmanan ,  Rakesh Hariharan ,  Lakshmanan Balasubramanian

IPC: G01R31/317 ,  G01R3/00

Abstract: A packaged electronic device has a die with a load circuit, a resistor and an analog to digital converter (ADC). The resistor is coupled between a supply node of the die and a power input of the load circuit. The ADC has a first input coupled to a first terminal of the resistor, and a second input coupled to a second terminal of the resistor to measure a voltage across the resistor while a supply voltage is applied to the supply node to determine a load current conducted by the load circuit. A method of manufacturing a packaged electronic device includes wafer processing to fabricate the load circuit, the resistor and the ADC on or in a die area of the wafer with the resistor coupled between the power input of the load circuit and the supply node of the die area.

公开(公告)号：US12026521B2

公开(公告)日：2024-07-02

申请号：US17521378

申请日：2021-11-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark Edward Wentroble ,  Anant Shankar Kamath ,  Rakesh Hariharan ,  Prajwala P ,  Suzanne Mary Vining

IPC: G06F13/00 ,  G06F1/3215 ,  G06F9/4401 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F9/4411 ,  G06F1/3215 ,  G06F13/382 ,  G06F13/4282 ,  G06F2213/0042

Abstract: A serial bus repeater includes first and second ports adapted to be coupled to respective devices. A first termination resistor network couples to the first port. A second termination resistor network couples to the second port. A squelch detect circuit couples to the first bus port and is configured to detect activity on the first bus and to generate a squelch signal responsive to detection of activity on the first port. A first state machine is configured to: determine an elapsed time during which the squelch signal indicates activity on the first port; determine that the elapsed time exceeds a first threshold; and, responsive to the determination that the elapsed time exceeds the first threshold, assert configuration signals to reconfigure the first and second termination resistor networks.

公开(公告)号：US11876518B2

公开(公告)日：2024-01-16

申请号：US17463829

申请日：2021-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rakesh Hariharan ,  Sumantha Manoor Madhyastha

IPC: H03K19/177 ,  G06F1/08 ,  H03K21/08 ,  G06F115/02

CPC classification number: H03K19/177 ,  G06F1/08 ,  H03K21/08 ,  G06F2115/02

Abstract: An system-on-a-chip (“SoC”) is provided. In some examples, the SoC includes a processor and a plurality of timer circuit blocks including at least a first timer circuit block and a second timer circuit block. Each of the plurality of timer circuit blocks may be selectively coupled by at least one of a first programmable matrix and a second programmable matrix. In some examples, the first programmable matrix may be configured to couple a second trigger input of the first timer circuit block with a first trigger output of the second timer circuit block. In some examples, the second programmable matrix is configured to couple a second fault input of the first timer circuit block with a first fault output of the second timer circuit block.

公开(公告)号：US11669475B2

公开(公告)日：2023-06-06

申请号：US17246137

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Anant Shankar Kamath ,  Rakesh Hariharan ,  Mark Edward Wentroble

IPC: G06F13/38 ,  H03K5/24 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/385 ,  G06F13/4072 ,  G06F13/4221 ,  H03K5/2472

Abstract: An isolating repeater and corresponding method for Universal Serial Bus (USB) communications. The isolating repeater includes, on either side of a galvanic isolation barrier, front end circuitry coupled to a pair of external terminals, a full speed (FS) transceiver adapted to drive and receive signals over one or more FS isolation channels, and a high speed (HS) transceiver adapted to drive signals over a one HS isolation channel and receive signals over another HS isolation channel. The front end circuitry encodes received signals corresponding to HS data into two-state signals for transmission over one HS isolation channel, and encodes received signals corresponding to HS signaling into two-state signals for transmission over one or more of the FS isolation channels. The front end circuitry on the other side of the isolation barrier decodes the two-state signals received over the one or more FS isolation channels and the two-state signals received over the HS isolation channel for transmission at its external terminals.

公开(公告)号：US11630797B2

公开(公告)日：2023-04-18

申请号：US17341089

申请日：2021-06-07

Applicant: Texas Instruments Incorporated

Inventor： Anant Shankar Kamath ,  Rakesh Hariharan ,  Vivekkumar Ramanlal Vadodariya ,  Soumi Paul ,  Mayank Garg

IPC: G06F13/42 ,  G06F1/3215 ,  G06F13/38

Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.