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公开(公告)号：US11018582B2
公开(公告)日：2021-05-25
申请号：US16399793
申请日：2019-04-30
Applicant: Texas Instruments Incorporated
Inventor： Saurav Bandyopadhyay , Michael G. Amaro , Michael Thomas DiRenzo , Thomas Matthew LaBella , Robert Allan Neidorff
Abstract: A circuit includes a first transistor and a second transistor coupled to the first transistor at a switch node and to a ground node. An estimator circuit receives a first signal to control an on and off state of the first transistor. The estimator circuit generates a second signal to control the on and off state of the second transistor. The second signal has a pulse width based on a pulse width of the first signal. A clocked comparator includes a clock input, a first input, and a second input. The first input receives a voltage indicative of a voltage of the switch node. The second input is coupled to a ground node. The clock input receives a third signal indicative of the second signal. The clocked comparator generates a comparator output signal. The estimator circuit adjusts the pulse width of the second signal based on the comparator output signal.
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公开(公告)号：US10468987B2
公开(公告)日：2019-11-05
申请号：US16241612
申请日：2019-01-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Matthew LaBella , Michael G. Amaro , Jeffrey Anthony Morroni
Abstract: Timing circuitry causes: a first closed signal on a first switch control output before a signal on a second switch control output changes from a second closed signal to a first open signal; the first switch control output to provide a second open signal after a first selected time after the second switch control output changes from the second closed signal to the first open signal; and a third switch control output to provide a third closed signal a second selected time after the first switch control output changes from the first closed signal to a third open signal. A beginning of the first closed signal to a beginning of the first open signal is based on a later of: a current through a switch connected to the second switch control output exceeding a threshold current; and a clocked time after the beginning of the first closed signal.
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3.发明授权公开(公告)号：US09654003B1
公开(公告)日：2017-05-16
申请号：US14982750
申请日：2015-12-29
Applicant: Texas Instruments Incorporated
Inventor： Thomas Matthew LaBella , Michael G. Amaro , Jeffrey Anthony Morroni
CPC classification number: H02M3/158 , H02M2001/0058 , Y02B70/1425 , Y02B70/1491
Abstract: In a method arrangement, providing a zero voltage transition circuit including an input node, an output node, a switch node, an output inductor coupling the switch node and output node, an output capacitor coupling the output node and ground, a first switch coupling the input node and switch node, a second switch coupling switch node and ground, a first auxiliary switch coupling the input node to an auxiliary node, a second auxiliary switch coupling the auxiliary node to ground, and an auxiliary inductor coupling the auxiliary node to the switch node; closing the first auxiliary switch to couple the input to the auxiliary node; subsequently, when a current is below a cutoff threshold, opening the second switch; after a first delay period, opening the first auxiliary switch and closing the second auxiliary switch; and after a second delay period, closing the first switch. Apparatus and additional method arrangements are disclosed.
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公开(公告)号：US20210050782A1
公开(公告)日：2021-02-18
申请号：US16860511
申请日：2020-04-28
Applicant: Texas Instruments Incorporated
Inventor： Saurav Bandyopadhyay , Thomas Matthew LaBella , Huy Le Nhat Nguyen , Michael G. Amaro , Robert Allan Neidorff
IPC: H02M3/158 , H03K17/082 , G06F1/26
Abstract: A switch-mode power supply circuit includes a low-side switching transistor, a high-side switching transistor, a low-side current sensing circuit, and a gate driver circuit. The low-side current sensing circuit is coupled to the low-side switching transistor and is configured to sense a current flowing through the low-side switching transistor. The gate driver circuit is coupled to the low-side current sensing circuit and the high-side switching transistor. The gate driver circuit is configured to generate a signal having a first drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being less than a threshold current, and to generate a signal having a second drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being greater than the threshold current. The first drive strength is greater than the second drive strength.
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5.发明申请公开(公告)号：US20200067410A1
公开(公告)日：2020-02-27
申请号：US16670638
申请日：2019-10-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Matthew LaBella , Michael G. Amaro , Jeffrey Anthony Morroni
Abstract: Timing circuitry causes: a first closed signal on a first switch control output before a signal on a second switch control output changes from a second closed signal to a first open signal; the first switch control output to provide a second open signal after a first selected time after the second switch control output changes from the second closed signal to the first open signal; and a third switch control output to provide a third closed signal a second selected time after the first switch control output changes from the first closed signal to a third open signal. A beginning of the first closed signal to a beginning of the first open signal is based on a later of: a current through a switch connected to the second switch control output exceeding a threshold current; and a clocked time after the beginning of the first closed signal.
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Patent Agency Ranking
公开(公告)号：US10177658B2
公开(公告)日：2019-01-08
申请号：US15350697
申请日：2016-11-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Matthew LaBella , Michael G. Amaro , Jeffrey Anthony Morroni
Abstract: Described examples include a method of controlling a power converter including executing a plurality of cycles. Each cycle includes turning on a first switch during a first period, the first switch coupled between a power supply and an output inductance; turning on a second switch during a second period, the second switch coupled between an output inductance and ground; turning on a third switch at a first time during the second period, the third switch coupled between the power supply and an auxiliary inductance; and turning on a fourth switch on at a third time after the second time, the fourth switch coupled the auxiliary inductance and ground. The second period ends at a third time period after the first time based on a later of an overlap time and a current through a switch connected to the second switch current handling terminal exceeding a threshold current.
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公开(公告)号：US09306458B2
公开(公告)日：2016-04-05
申请号：US14318307
申请日：2014-06-27
Applicant: Texas Instruments Incorporated
Inventor： Joseph Maurice Khayat , Ramanathan Ramani , Michael G. Amaro
IPC: H02M3/158
CPC classification number: H02M3/158
Abstract: A power circuit combination includes a series capacitor buck converter including a first half-bridge including a first high side power switch (HSA), first low side power switch (LSA) and a second half-bridge. A transfer capacitor (Ct) is connected in series with HSA and LSA, and between the first and second half-bridges. An adaptive HS driver circuit has an output coupled to a gate of HSA and includes a power supply circuit including a summing circuitry that dynamically outputs a variable power supply level (VGX) based on a fixed voltage and a voltage across Ct, a buffer driver, and a boost capacitor (CA) across the buffer driver. VGX is coupled to a positive terminal of CA. The power supply circuit is configured so that as a voltage across Ct varies, VGX adjusts so that a voltage across CA is changed less than a change in voltage across Ct.
Abstract translation: 电源电路组合包括串联电容器降压转换器，其包括包括第一高侧功率开关（HSA），第一低侧功率开关（LSA）和第二半桥的第一半桥。 传输电容器（Ct）与HSA和LSA以及第一和第二半桥之间串联连接。 自适应HS驱动器电路具有耦合到HSA的栅极的输出，并且包括电源电路，其包括基于固定电压和跨越Ct的电压来动态地输出可变电源电平（VGX）的求和电路，缓冲器驱动器， 和缓冲驱动器上的升压电容（CA）。 VGX耦合到CA的正端子。 电源电路被配置为使得当Ct上的电压变化时，VGX进行调整，使得CA两端的电压变化小于Ct两端的电压变化。
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公开(公告)号：US20150002115A1
公开(公告)日：2015-01-01
申请号：US14319964
申请日：2014-06-30
Applicant: Texas Instruments Incorporated
Inventor： Pradeep S. Shenoy , Michael G. Amaro
IPC: H02M3/158
CPC classification number: H02M3/158 , H02M3/1584
Abstract: A series-capacitor adaptively switched power conversion system includes, for example, a series-capacitor buck converter overlapping controller. The series-capacitor buck converter overlapping controller is arranged to provide reduced switching losses and improved system efficiency while the switched power conversion system is operating in a discontinuous conduction mode (DCM). While operating in the DCM, the series-capacitor buck converter overlapping controller generates precisely controlled frequency modulated waveforms that are adapted to independently drive control switches of one or more power converters. The series-capacitor buck converter overlapping controller is arranged to reduce (or eliminate) negative inductor current (and the associated conduction loss) that can be present in multiphase (two or more phases) series-capacitor buck converters.
Abstract translation: 串联电容器自适应切换电力转换系统包括例如串联电容降压转换器重叠控制器。 串联电容降压转换器重叠控制器布置成在开关电源转换系统工作在不连续导通模式（DCM）时提供降低的开关损耗并提高系统效率。 在DCM中工作时，串联电容降压转换器重叠控制器产生精确控制的调频波形，适用于独立驱动一个或多个功率转换器的控制开关。 串联电容降压转换器重叠控制器被布置为减少（或消除）可以存在于多相（两相或更多相）串联电容降压转换器中的负电感器电流（和相关的导通损耗）。
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公开(公告)号：US11211865B2
公开(公告)日：2021-12-28
申请号：US16799112
申请日：2020-02-24
Applicant: Texas Instruments Incorporated
Inventor： Joseph Maurice Khayat , Sergio Carlo-Rodriquez , Michael G. Amaro , Ramanathan Ramani , Pradeep S. Shenoy
Abstract: A series capacitor buck converter includes a first half-bridge circuit including a first high side power switch (HSA) and first low side power switch (LSA) connected in series having a first switching node (SWA) therebetween which drives a first output inductor, a second half-bridge circuit including a second HS power switch (HSB) and second LS power switch (LSB) connected in series having a second switching node (SWB) therebetween which drives a second output inductor. A transfer capacitor (Ct) is connected in series with HSA and LSA and between the first and second half-bridge circuits. A first current source is coupled for precharging Ct with a charging current (I_in) and a second current source is coupled to Ct for providing an output current (I_out). A feedback network providing negative feedback forces I_out to match I_in.
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10.发明申请公开(公告)号：US20170302177A1
公开(公告)日：2017-10-19
申请号：US15350697
申请日：2016-11-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Thomas Matthew LaBella , Michael G. Amaro , Jeffrey Anthony Morroni
CPC classification number: H02M3/158 , H02M1/08 , H02M2001/0009 , H02M2001/0032 , H02M2001/0058 , Y02B70/1491 , Y02B70/16
Abstract: Described examples include a method of controlling a power converter including executing a plurality of cycles. Each cycle includes turning on a first switch during a first period, the first switch coupled between a power supply and an output inductance; turning on a second switch during a second period, the second switch coupled between an output inductance and ground; turning on a third switch at a first time during the second period, the third switch coupled between the power supply and an auxiliary inductance; and turning on a fourth switch on at a third time after the second time, the fourth switch coupled the auxiliary inductance and ground. The second period ends at a third time period after the first time based on a later of an overlap time and a current through a switch connected to the second switch current handling terminal exceeding a threshold current.
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