公开(公告)号：US20180204917A1

公开(公告)日：2018-07-19

申请号：US15601591

申请日：2017-05-22

Applicant: Texas Instruments Incorporated

Inventor： Furen LIN ,  Frank BAIOCCHI ,  Haian LIN ,  Yunlong LIU ,  Lark LIU ,  Wei SONG ,  ZiQiang ZHAO

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/41741 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41775 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7834

Abstract: A power MOSFET IC device including an array of MOSFET cells formed in a semiconductor substrate. The array of MOSFET cells comprises an interior region of interior MOSFET cells and an outer edge region of peripheral MOSFET cells, each interior MOSFET cell of the interior region of the array comprising a pair of interior MOSFET devices coupled to each other at a common drain contact. In an example embodiment, each interior MOSFET device includes a source contact (SCT) trench extended into a substrate contact region of the semiconductor substrate. The SCT trench is provided with a length less than a linear portion of a polysilicon gate of the interior MOSFET device, wherein the SCT trench is aligned to the polysilicon gate having a curvilinear layout geometry.

公开(公告)号：US20140183622A1

公开(公告)日：2014-07-03

申请号：US14135661

申请日：2013-12-20

Applicant: Texas Instruments Incorporated

Inventor： Haian LIN ,  Shuming XU ,  Jacek KOREC

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7806 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66712 ,  H01L29/872

Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.

Abstract translation: 通过在垂直功率MOSFET的扩展漏极上形成源电极形成包含具有平面栅极和集成肖特基二极管的垂直功率MOSFET的半导体器件，以形成肖特基二极管并在垂直的源极区域上形成源电极 功率MOSFET。 肖特基二极管通过源电极连接到源极区域。 漏电极形成在半导体器件的衬底的底部。 肖特基二极管通过垂直功率MOSFET的扩展漏极连接到漏电极。

公开(公告)号：US20200220007A1

公开(公告)日：2020-07-09

申请号：US16821165

申请日：2020-03-17

Applicant: Texas Instruments Incorporated

Inventor： Haian LIN ,  Shuming XU ,  Jacek KOREC

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/47 ,  H01L29/872 ,  H01L29/08

Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.

公开(公告)号：US20150214222A1

公开(公告)日：2015-07-30

申请号：US14608391

申请日：2015-01-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jun WANG ,  Frank BAIOCCHI ,  Haian LIN

IPC: H01L27/088 ,  H01L29/78 ,  H02M3/155

CPC classification number: H01L27/088 ,  H01L21/26533 ,  H01L21/761 ,  H01L21/823493 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/7816 ,  H01L29/7835 ,  H02M3/1588 ,  Y02B70/1466

Abstract: An integrated semiconductor transistor chip for use in a buck converter includes a high side transistor formed on the chip and comprising a laterally diffused metal oxide semiconductor (LDMOS) transistor and a low side transistor formed on the chip and comprising a source down metal oxide semiconductor field effect transistor (MOSFET). The chip also includes a substrate of the chip for use as a source for the low side transistor and an n-doped well for isolation of the high side transistor from the source of the low side transistor.

Abstract translation: 用于降压转换器的集成半导体晶体管芯片包括形成在芯片上并包括横向扩散的金属氧化物半导体（LDMOS）晶体管的高侧晶体管和形成在芯片上的低侧晶体管，并且包括源极下行金属氧化物半导体场 效应晶体管（MOSFET）。 该芯片还包括用作低侧晶体管的源极的芯片的衬底和用于将高侧晶体管与低侧晶体管的源极隔离的n掺杂阱。

公开(公告)号：US20200328275A1

公开(公告)日：2020-10-15

申请号：US16384700

申请日：2019-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian LIN ,  Frank Alexander BAIOCCHI ,  Seetharaman SRIDHAR

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06

Abstract: In some examples, a semiconductor device, comprises a semiconductor substrate; an epitaxial layer having a top side disposed on the semiconductor substrate, wherein the epitaxial layer has a source implant region, a drain implant region, a first doped region, and a second doped region, wherein the first doped region is adjacent to the source implant region and the second doped region is adjacent to the drain implant region, wherein the top side has a sloped surface over the second doped region; a gate electrode supported by the top side; a source electrode in contact with the source implant region; and a drain electrode in contact with the drain implant region.

公开(公告)号：US20190004201A1

公开(公告)日：2019-01-03

申请号：US16101867

申请日：2018-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen LIN ,  Frank BAIOCCHI ,  Haian LIN ,  Yunlong LIU ,  Lark LIU ,  Wei SONG ,  ZiQiang ZHAO

IPC: G01V1/38 ,  G01V1/24 ,  G01V1/16 ,  G01V1/18

Abstract: A method of forming an electronic device includes forming a plurality of closed loops over a semiconductor substrate. Each closed loop has a first and a second polysilicon gate structure joined at first and second ends. Each closed loop includes an inner portion and an end portion. In the inner portion the first polysilicon gate structure runs about parallel to the second polysilicon gate structure. In the outer portion the first polysilicon gate structure converges with the second polysilicon gate structure. The method further includes forming a plurality of trench contacts. Each of the trench contacts is located between a respective pair of closed loops, passes through an epitaxial layer and contacts the substrate. The length of the trench contacts is no greater than the length of the inner portions.