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公开(公告)号：US20050139900A1
公开(公告)日：2005-06-30
申请号：US11019304
申请日：2004-12-23
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/76 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42336 , H01L29/7883
摘要： The present invention provides a non-volatile memory device and fabricating method thereof, in which a height of a floating gate conductor layer pattern is sustained without lowering a degree of integration and by which a coupling ratio is raised. The present invention includes a trench type device isolation layer defining an active area within a semiconductor substrate, a recess in an upper part of the device isolation layer to have a prescribed depth, a tunnel oxide layer on the active area of the semiconductor substrate, a floating gate conductor layer pattern on the tunnel oxide layer, a conductive floating spacer layer provided to a sidewall of the floating gate conductor layer pattern and a sidewall of the recess, a gate-to-gate insulating layer on the floating fate conductor layer pattern and the conductive floating spacer layer, and a control gate conductor layer on the gate-to-gate insulating layer.
摘要翻译： 本发明提供了一种非易失性存储器件及其制造方法，其中浮动栅极导体层图案的高度在不降低积分度的情况下被维持并且耦合比率被提高。 本发明包括限定半导体衬底内的有源区域的沟槽型器件隔离层，在器件隔离层的上部具有规定深度的凹部，半导体衬底的有源区上的隧道氧化物层， 在所述隧道氧化物层上的浮栅导体层图案，设置在所述浮栅导体层图案的侧壁和所述凹部的侧壁的导电浮动间隔层，所述浮置导体层图案上的栅极至栅极绝缘层，以及 导电浮动间隔层，以及栅极至栅极绝缘层上的控制栅极导体层。
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公开(公告)号：US20050101089A1
公开(公告)日：2005-05-12
申请号：US11004301
申请日：2004-12-03
申请人： Jum Kim , Sung Jung , Jung Ahn , Young Shin , Young Lee
发明人： Jum Kim , Sung Jung , Jung Ahn , Young Shin , Young Lee
IPC分类号： H01L21/762 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/44 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/76235
摘要： A method of manufacturing a flash memory cell. The method includes controlling a wall sacrificial oxidization process, a wall oxidization process and a cleaning process of a trench insulating film that are performed before/after a process of forming the trench insulating film for burying a trench to etch the trench insulating film to a desired space. Therefore, it is possible to secure the coupling ratio of a floating gate by maximum and implement a device of a smaller size.
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公开(公告)号：US20050139901A1
公开(公告)日：2005-06-30
申请号：US11019299
申请日：2004-12-23
IPC分类号： H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, a first conductive type well arranged between the at least two trench isolation layers to have a second depth smaller than the first depth, a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between, an ONO layer on the channel region of the semiconductor substrate, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer, and a wordline conductor layer on the ONO layer.
摘要翻译： 本发明提供了一种非易失性存储器件及其制造方法，通过该非易失性存储器件可以降低电池尺寸，尽管电池集成度高，并且器件制造方便。 本发明包括布置在半导体衬底的器件隔离区域中的至少两个沟槽隔离层，每个具有第一深度，第一导电类型阱布置在所述至少两个沟槽隔离层之间，以具有小于第一深度的第二深度 第二导电型源极区域和第二导电型漏极区域，布置在第一导电类型阱的规定的上部中，通过其间的沟道区域彼此分离，在该沟道区域上的ONO层 半导体衬底，ONO层包括低氧化物层，氮化物层和上部氧化物层，以及ONO层上的字线导体层。
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4.发明申请公开(公告)号：US20050074949A1
公开(公告)日：2005-04-07
申请号：US10954488
申请日：2004-10-01
IPC分类号： H01L21/76 , H01L21/336 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for fabricating the semiconductor device includes forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the field oxide regions; and forming gate lines on the field oxide regions and the gate oxide lines, the gate lines being substantially perpendicular to the field oxide regions, wherein forming the gate lines also includes forming recesses in the semiconductor substrate between the gate lines, the recesses exposing portions of the semiconductor substrate.
摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成线性场氧化物区域; 在所述场氧化物区域之间的所述半导体衬底上形成栅极氧化物线; 并且在场氧化物区域和栅极氧化物线上形成栅极线，栅极线基本上垂直于场氧化物区域，其中形成栅极线还包括在栅极线之间的半导体衬底中形成凹槽， 半导体衬底。
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公开(公告)号：US20050202633A1
公开(公告)日：2005-09-15
申请号：US11123004
申请日：2005-05-06
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , H01L29/40114 , H01L29/42324 , H01L29/6656
摘要： The present invention relates to a method of manufacturing a nonvolatile memory cell. The present invention uses tungsten (W) as an upper layer of a control gate electrode in order to integrate the memory cell and performs an ion implantation process for forming a source region and a drain region before a selective oxidization process that is performed to prevent abnormal oxidization of tungsten (W). Therefore, the present invention can reduce a RC delay time of word lines depending on integration of the memory cell and also secure a given distance between a silicon substrate and a tunnel oxide film. As a result, the present invention can solve a data retention problem of the flash memory.
摘要翻译： 本发明涉及一种制造非易失性存储单元的方法。 本发明使用钨（W）作为控制栅电极的上层，以便整合存储单元，并且在进行选择性氧化处理之前进行用于形成源区和漏区的离子注入工艺，以防止异常 钨的氧化（W）。 因此，本发明可以根据存储单元的积分来减少字线的RC延迟时间，并且还可以确保硅衬底和隧道氧化物膜之间的给定距离。 结果，本发明可以解决闪速存储器的数据保留问题。
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公开(公告)号：US20050142725A1
公开(公告)日：2005-06-30
申请号：US11019301
申请日：2004-12-23
IPC分类号： H01L21/762 , H01L21/8247 , H01L27/115 , H01L21/8238 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The present invention provides a method of fabricating a non-volatile memory device, in which trench isolation can be achieved using an insulating layer that needs no separate removal process. The present invention includes sequentially forming a first insulating layer, a first conductor layer, and a second insulating layer on a semiconductor substrate, patterning the second insulating layer, the first conductor layer, and the first insulating layer to expose a prescribed portion of the semiconductor substrate, forming a trench having a prescribed depth in the semiconductor substrate by removing the exposed portion of the semiconductor substrate, forming a third insulating layer on the second insulating layer including the trench, planarizing the third insulating layer to remove the second insulating layer until the first conductor layer is exposed, forming a fourth insulating layer on the exposed first conductor layer and the remaining third insulating layer, and forming a second conductor layer on the fourth insulating layer.
摘要翻译： 本发明提供一种制造非易失性存储器件的方法，其中可以使用不需要单独去除工艺的绝缘层来实现沟槽隔离。 本发明包括在半导体衬底上依次形成第一绝缘层，第一导体层和第二绝缘层，图案化第二绝缘层，第一导体层和第一绝缘层以暴露半导体的规定部分 衬底，通过去除半导体衬底的暴露部分在半导体衬底中形成具有规定深度的沟槽，在包括沟槽的第二绝缘层上形成第三绝缘层，平坦化第三绝缘层以移除第二绝缘层，直到 暴露第一导体层，在暴露的第一导体层和剩余的第三绝缘层上形成第四绝缘层，并在第四绝缘层上形成第二导体层。
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公开(公告)号：US20070131996A1
公开(公告)日：2007-06-14
申请号：US11701484
申请日：2007-02-02
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, a first conductive type well arranged between the at least two trench isolation layers to have a second depth smaller than the first depth, a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between, an ONO layer on the channel region of the semiconductor substrate, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer, and a wordline conductor layer on the ONO layer.
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公开(公告)号：US20050142745A1
公开(公告)日：2005-06-30
申请号：US11019302
申请日：2004-12-23
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer. The present invention includes forming a mask layer pattern on a semiconductor substrate to expose a device isolation area but to cover an active area thereof, the mask layer pattern comprising a first insulating layer pattern and a second insulating layer pattern stacked thereon, forming a trench in the semiconductor substrate corresponding to the device isolation area, removing an exposed portion of the first insulating layer pattern enough to expose a portion of the semiconductor substrate in the active area adjacent to the trench, forming a sidewall oxide layer on an inside of the trench and the exposed portion of the semiconductor substrate, filling up the trench with a third insulating layer to cover the sidewall oxide layer, and removing the mask layer pattern.
摘要翻译： 本发明提供了一种闪速存储器件中的沟槽隔离方法，通过这种方法，在沟槽隔离层的边缘附近形成厚的衬垫氧化物层，增强了器件的稳定性和可靠性。 本发明包括在半导体衬底上形成掩模层图案以暴露器件隔离区域而覆盖其有效区域，掩模层图案包括第一绝缘层图案和叠置在其上的第二绝缘层图案，形成沟槽 所述半导体衬底对应于所述器件隔离区域，去除所述第一绝缘层图案的暴露部分以足以暴露所述半导体衬底在与所述沟槽相邻的有源区域中的一部分，在所述沟槽的内部形成侧壁氧化物层，以及 半导体衬底的暴露部分，用第三绝缘层填充沟槽以覆盖侧壁氧化物层，以及去除掩模层图案。
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公开(公告)号：US20050139916A1
公开(公告)日：2005-06-30
申请号：US11020276
申请日：2004-12-27
IPC分类号： H01L29/78 , H01L29/417 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/41775
摘要： A high voltage semiconductor device and fabricating method thereof, enable a high breakdown voltage to be provided from a surface area without forming a dual spacer layer. The semiconductor device includes a semiconductor substrate having source/drain regions separated from each other by a channel region in-between, a gate insulating layer pattern on the channel region, a gate conductor layer pattern on the gate insulating layer, a sidewall insulating layer provided on a sidewall of the gate conductor layer pattern, a salicide suppress layer pattern covering partial, but not entire, surfaces of the source/drain regions, and covering the sidewall insulating layer, and the gate conductor layer pattern, and a metal salicide layer on remaining portions surfaces of the source/drain regions that are not covered with the salicide suppress layer pattern.
摘要翻译： 高压半导体器件及其制造方法能够从表面区域提供高的击穿电压而不形成双间隔层。 半导体器件包括具有源极/漏极区域的半导体衬底，沟道区域之间的沟道区域彼此分离，沟道区域上的栅极绝缘层图案，栅极绝缘层上的栅极导体层图案，提供的侧壁绝缘层 在栅极导体层图案的侧壁上，覆盖源极/漏极区域的部分但不是整个表面并且覆盖侧壁绝缘层和栅极导体层图案以及金属硅化物层的自对准硅化物抑制层图案 未被自对准硅化物抑制层图案覆盖的源/漏区的剩余部分表面。
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10.发明申请Device isolation method of semiconductor memory device and flash memory device fabricating method using the same 有权半导体存储器件的器件隔离方法及其使用的闪存器件制造方法公开(公告)号：US20050142796A1
公开(公告)日：2005-06-30
申请号：US11019352
申请日：2004-12-23
IPC分类号： H01L21/762 , H01L21/8247 , H01L27/115 , H01L21/76
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/115
摘要： The present invention provides a device isolation method of a semiconductor memory device and flash memory device fabricating method using the same, which can prevent a bridge occurrence between cells. The present invention includes forming a nitride layer pattern defining a trench forming area on a semiconductor substrate, forming a spacer on a sidewall of the nitride layer pattern, forming a trench in the semiconductor layer by removing a portion of the semiconductor layer using the nitride layer pattern and the spacer as an etch mask, forming a device isolation layer filling up the trench, removing the nitride layer pattern and the spacer to complete the device isolation layer, forming a conductor layer over the substrate including the device isolation layer, planarizing the conductor layer and the device isolation layer to lie in a same plane, and forming an insulating layer over the substrate.
摘要翻译： 本发明提供了一种半导体存储器件的器件隔离方法和使用该半导体存储器件的闪存器件制造方法，其可以防止单元之间的桥接发生。 本发明包括在半导体衬底上形成限定沟槽形成区域的氮化物层图案，在氮化物层图案的侧壁上形成间隔物，通过使用氮化物层去除半导体层的一部分，在半导体层中形成沟槽 形成作为蚀刻掩模的间隔物，形成填充沟槽的器件隔离层，去除氮化物层图案和间隔物以完成器件隔离层，在包括器件隔离层的衬底上形成导体层，平坦化导体 层和器件隔离层位于同一平面上，并在衬底上形成绝缘层。
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