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公开(公告)号：US12003870B2
公开(公告)日：2024-06-04
申请号：US17721801
申请日：2022-04-15
Applicant: Sony Semiconductor Solutions Corporation
Inventor： Pooria Mostafalu , Frederick T. Brady , Sungin Han , Hongyi Mi
Abstract: Binning in a hybrid pixel structure of image pixels and event vision sensor (EVS) pixels. In one embodiment, the imaging sensor includes a pixel array including a plurality of pixel circuits and a plurality of binning transistors. A first portion of the plurality of pixel circuits individually includes an intensity photodiode. A second portion of the plurality of pixel circuits individually includes an event vision sensor (EVS) photodiode. The plurality of binning transistors is configured to bin together at least one of the first portion or the second portion.
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Patent Agency Ranking
公开(公告)号：US11979675B2
公开(公告)日：2024-05-07
申请号：US17728190
申请日：2022-04-25
Applicant: Sony Semiconductor Solutions Corporation
Inventor： Hongyi Mi , Frederick T. Brady , Sungin Han , Pooria Mostafalu
IPC: H04N25/702 , H01L27/146 , H04N25/75 , H04N25/79
CPC classification number: H04N25/702 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/14634 , H01L27/14636 , H01L27/14645 , H04N25/79 , H04N25/75
Abstract: Image sensing devices are disclosed. In one example, an image sensing device includes a pixel unit cell with both event sensing (EVS) pixels and imaging pixels. The EVS and imaging pixels are configured to include event sensing and imaging pixel transistors formed in the same transistor layer of an integrated circuit assembly that also includes the photodiodes of the EVS and imaging pixels. The photodiodes are separated by a rear deep trench isolation (RDTI), and the EVS and imaging pixel transistors are arranged along (e.g., underneath) boundary areas formed by the RDTI, maximizing the space available for the photodiodes and economizing on wiring requirements for the EVS and imaging pixels.
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公开(公告)号：US20230326952A1
公开(公告)日：2023-10-12
申请号：US17702474
申请日：2022-03-23
Applicant: Sony Semiconductor Solutions Corporation
Inventor： Hongyi Mi , Frederick T. Brady , Sungin Han , Pooria Mostafalu
IPC: H04N5/357 , H01L27/146
CPC classification number: H01L27/14643 , H01L27/14612 , H01L27/14621 , H01L27/14636 , H01L27/14689 , H04N5/357
Abstract: A pixelated image sensor capable of simultaneously supporting an EVS mode and an image-frame capture mode of operation. An individual pixel of the sensor comprises two distinct sets of subpixels involved in the two modes, respectively, and at least two corresponding, functionally different and independent electrical circuits. The metal interconnect structure of the image-sensor IC is implemented using a wiring topology in which spatial overlap between the wirings of the two electrical circuits is optimized (e.g., minimized) to reduce inter-circuit crosstalk when the two circuits are active at the same time. Such wiring topology may be beneficial, e.g., due to the resulting improvements in the image quality for both operating modes.
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公开(公告)号：US11929383B2
公开(公告)日：2024-03-12
申请号：US17702474
申请日：2022-03-23
Applicant: Sony Semiconductor Solutions Corporation
Inventor： Hongyi Mi , Frederick T. Brady , Sungin Han , Pooria Mostafalu
IPC: H01L27/146 , H04N25/60
CPC classification number: H01L27/14643 , H01L27/14612 , H01L27/14621 , H01L27/14636 , H01L27/14689 , H04N25/60
Abstract: A pixelated image sensor capable of simultaneously supporting an EVS mode and an image-frame capture mode of operation. An individual pixel of the sensor comprises two distinct sets of subpixels involved in the two modes, respectively, and at least two corresponding, functionally different and independent electrical circuits. The metal interconnect structure of the image-sensor IC is implemented using a wiring topology in which spatial overlap between the wirings of the two electrical circuits is optimized (e.g., minimized) to reduce inter-circuit crosstalk when the two circuits are active at the same time. Such wiring topology may be beneficial, e.g., due to the resulting improvements in the image quality for both operating modes.
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公开(公告)号：US20230345147A1
公开(公告)日：2023-10-26
申请号：US17728190
申请日：2022-04-25
Applicant: Sony Semiconductor Solutions Corporation
Inventor： Hongyi Mi , Frederick T. Brady , Sungin Han , Pooria Mostafalu
IPC: H04N5/369 , H01L27/146
CPC classification number: H04N5/3696 , H04N5/379 , H01L27/14645 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/14636 , H01L27/14634 , H04N5/378
Abstract: Image sensing devices are disclosed. In one example, an image sensing device includes a pixel unit cell with both event sensing (EVS) pixels and imaging pixels. The EVS and imaging pixels are configured to include event sensing and imaging pixel transistors formed in the same transistor layer of an integrated circuit assembly that also includes the photodiodes of the EVS and imaging pixels. The photodiodes are separated by a rear deep trench isolation (RDTI), and the EVS and imaging pixel transistors are arranged along (e.g., underneath) boundary areas formed by the RDTI, maximizing the space available for the photodiodes and economizing on wiring requirements for the EVS and imaging pixels.
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6.发明公开公开(公告)号：US20230336881A1
公开(公告)日：2023-10-19
申请号：US17721801
申请日：2022-04-15
Applicant: Sony Semiconductor Solutions Corporation
Inventor： Pooria Mostafalu , Frederick T. Brady , Sungin Han , Hongyi Mi
IPC: H04N5/347 , H04N5/3745 , H04N5/343
CPC classification number: H04N5/347 , H04N5/3745 , H04N5/343
Abstract: Binning in a hybrid pixel structure of image pixels and event vision sensor (EVS) pixels. In one embodiment, the imaging sensor includes a pixel array including a plurality of pixel circuits and a plurality of binning transistors. A first portion of the plurality of pixel circuits individually includes an intensity photodiode. A second portion of the plurality of pixel circuits individually includes an event vision sensor (EVS) photodiode. The plurality of binning transistors is configured to bin together at least one of the first portion or the second portion.
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