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公开(公告)号：US20140189169A1
公开(公告)日：2014-07-03
申请号：US13731278
申请日：2012-12-31
Applicant: SILICON LABORATORIES INC.
Inventor： Timothy E. Litch , Paul I. Zavalney
IPC: G06F13/28
CPC classification number: G06F13/28
Abstract: An apparatus includes an integrated circuit that includes a processing core and a direct memory access (DMA) engine. The DMA engine is adapted to process descriptors to control DMA communications. The descriptors contain data indicating communication endpoints that are associated with the DMA communications. The DMA engine is adapted to use other data contained in at least one of the descriptors to control branching of descriptor execution among multiple execution paths.
Abstract translation: 一种装置包括集成电路，其包括处理核心和直接存储器存取（DMA）引擎。 DMA引擎适用于处理描述符以控制DMA通信。 描述符包含指示与DMA通信相关联的通信端点的数据。 DMA引擎适于使用包含在至少一个描述符中的其他数据来控制多个执行路径之间的描述符执行的分支。
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公开(公告)号：US20140266336A1
公开(公告)日：2014-09-18
申请号：US13832708
申请日：2013-03-15
Applicant: SILICON LABORATORIES INC.
Inventor： Imranul Islam , Axen Thomsen , Paul I. Zavalney
IPC: H03L7/06
CPC classification number: H03L7/0816 , H03L7/0814
Abstract: A method includes generating one of a first clock signal and a second clock signal from the other clock signal. The first clock signal is configured to be used to synchronize an operation of an analog system, and the second clock signal is configured to be used to synchronize an operation of a digital system. The method includes using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal; and the method includes controlling a delay element of the digital system to regulate the timing based on the measurement by the phase detector to suppress noise in the analog system.
Abstract translation: 一种方法包括从另一个时钟信号产生第一时钟信号和第二时钟信号中的一个。 第一时钟信号被配置为用于同步模拟系统的操作，并且第二时钟信号被配置为用于同步数字系统的操作。 该方法包括使用模拟系统的相位检测器来测量相对于第二时钟信号的第一时钟信号的定时; 并且该方法包括控制数字系统的延迟元件，以基于相位检测器的测量来调节定时，以抑制模拟系统中的噪声。
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公开(公告)号：US09256558B2
公开(公告)日：2016-02-09
申请号：US13928487
申请日：2013-06-27
Applicant: SILICON LABORATORIES INC.
Inventor： Timothy E. Litch , Paul I. Zavalney , Paul Zucker
IPC: G06F13/28
CPC classification number: G06F13/28
Abstract: A method includes processing descriptors to control a direct memory access (DMA) channel. The method includes synchronizing at least part of the processing, which includes processing a first descriptor of the descriptors to cause the execution to selectively pause based on a trigger value.
Abstract translation: 一种方法包括处理描述符以控制直接存储器存取（DMA）通道。 该方法包括同步处理的至少一部分，其包括处理描述符的第一描述符，以使执行基于触发值选择性地暂停。
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公开(公告)号：US09083354B2
公开(公告)日：2015-07-14
申请号：US13832708
申请日：2013-03-15
Applicant: SILICON LABORATORIES INC.
Inventor： Imranul Islam , Axel Thomsen , Paul I. Zavalney
CPC classification number: H03L7/0816 , H03L7/0814
Abstract: A method includes generating one of a first clock signal and a second clock signal from the other clock signal. The first clock signal is configured to be used to synchronize an operation of an analog system, and the second clock signal is configured to be used to synchronize an operation of a digital system. The method includes using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal; and the method includes controlling a delay element of the digital system to regulate the timing based on the measurement by the phase detector to suppress noise in the analog system.
Abstract translation: 一种方法包括从另一个时钟信号产生第一时钟信号和第二时钟信号中的一个。 第一时钟信号被配置为用于同步模拟系统的操作，并且第二时钟信号被配置为用于同步数字系统的操作。 该方法包括使用模拟系统的相位检测器来测量相对于第二时钟信号的第一时钟信号的定时; 并且该方法包括控制数字系统的延迟元件，以基于相位检测器的测量来调节定时，以抑制模拟系统中的噪声。
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公开(公告)号：US20140189162A1
公开(公告)日：2014-07-03
申请号：US13731253
申请日：2012-12-31
Applicant: SILICON LABORATORIES INC.
Inventor： Xiaohui Wang , Paul I. Zavalney
CPC classification number: G06F13/28 , G06F13/4221 , H02M1/38 , H02M7/5395 , H02M2001/0012
Abstract: An apparatus includes an input/output (I/O) interface circuit that includes a memory and a controller. The memory stores a plurality of commands to regulate an input/output (I/O) interface. The commands indicate at least one I/O state of at least one I/O terminal of the I/O interface circuit and a time duration that is associated with the I/O state. The controller executes the commands to place the I/O interface in the the I/O state(s) in a predetermined sequence.
Abstract translation: 一种装置包括包括存储器和控制器的输入/输出（I / O）接口电路。 存储器存储多个命令以调节输入/输出（I / O）接口。 这些命令指示I / O接口电路的至少一个I / O端子的至少一个I / O状态和与I / O状态相关联的持续时间。 控制器执行命令，以预定的顺序将I / O接口置于I / O状态。
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Patent Agency Ranking
公开(公告)号：US20190238166A1
公开(公告)日：2019-08-01
申请号：US15883232
申请日：2018-01-30
Applicant: Silicon Laboratories Inc.
Inventor： Phillip Matthews , Paul I. Zavalney , John M. Khoury , Karma S. Bhutia
Abstract: Systems and methods are disclosed for spur mitigation for pulse signal drivers in radio frequency (RF) devices. An RF integrated circuit includes RF circuitry and analog-to-digital (ADC) circuitry. The RF circuitry operates using a local oscillator (LO) clock to receive and/or transmit RF signals, and the ADC circuitry samples one or more analog input signals and has internal timing based upon a raw digital clock. A retime circuit receives the raw digital clock and the LO clock and has a retimed clock as an output. The retimed clock represents the raw digital clock retimed with the LO clock. While other digital circuitry is timed using the raw digital clock, one or more drivers are timed by the retimed clock and provide pulse output signals to output pads. Having the drivers timed with the retimed clock and other digital circuitry timed with the raw digital clock improves overall performance.
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7.发明授权System method for regulating an input/output interface by sampling during a time duration associated with I/O states 有权用于通过在与I / O状态相关的持续时间内采样来调节输入/输出接口的系统方法公开(公告)号：US08954632B2
公开(公告)日：2015-02-10
申请号：US13731253
申请日：2012-12-31
Applicant: Silicon Laboratories Inc.
Inventor： Xiaohui Wang , Paul I. Zavalney
CPC classification number: G06F13/28 , G06F13/4221 , H02M1/38 , H02M7/5395 , H02M2001/0012
Abstract: An apparatus includes an input/output (I/O) interface circuit that includes a memory and a controller. The memory stores a plurality of commands to regulate an input/output (I/O) interface. The commands indicate at least one I/O state of at least one I/O terminal of the I/O interface circuit and a time duration that is associated with the I/O state. The controller executes the commands to place the I/O interface in the the I/O state(s) in a predetermined sequence.
Abstract translation: 一种装置包括包括存储器和控制器的输入/输出（I / O）接口电路。 存储器存储多个命令以调节输入/输出（I / O）接口。 这些命令指示I / O接口电路的至少一个I / O端子的至少一个I / O状态和与I / O状态相关联的持续时间。 控制器执行命令，以预定的顺序将I / O接口置于I / O状态。
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公开(公告)号：US20150006765A1
公开(公告)日：2015-01-01
申请号：US13928487
申请日：2013-06-27
Applicant: SILICON LABORATORIES INC.
Inventor： Timothy E. Litch , Paul I. Zavalney , Paul Zucker
IPC: G06F13/28
CPC classification number: G06F13/28
Abstract: A method includes processing descriptors to control a direct memory access (DMA) channel. The method includes synchronizing at least part of the processing, which includes processing a first descriptor of the descriptors to cause the execution to selectively pause based on a trigger value.
Abstract translation: 一种方法包括处理描述符以控制直接存储器存取（DMA）通道。 该方法包括同步处理的至少一部分，其包括处理描述符的第一描述符，以使执行基于触发值选择性地暂停。
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公开(公告)号：US10461787B2
公开(公告)日：2019-10-29
申请号：US15883232
申请日：2018-01-30
Applicant: Silicon Laboratories Inc.
Inventor： Phillip Matthews , Paul I. Zavalney , John M. Khoury , Karma S. Bhutia
Abstract: Systems and methods are disclosed for spur mitigation for pulse signal drivers in radio frequency (RF) devices. An RF integrated circuit includes RF circuitry and analog-to-digital (ADC) circuitry. The RF circuitry operates using a local oscillator (LO) clock to receive and/or transmit RF signals, and the ADC circuitry samples one or more analog input signals and has internal timing based upon a raw digital clock. A retime circuit receives the raw digital clock and the LO clock and has a retimed clock as an output. The retimed clock represents the raw digital clock retimed with the LO clock. While other digital circuitry is timed using the raw digital clock, one or more drivers are timed by the retimed clock and provide pulse output signals to output pads. Having the drivers timed with the retimed clock and other digital circuitry timed with the raw digital clock improves overall performance.
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10.发明授权System and method for regulating direct memory access descriptor among multiple execution paths by using a link to define order of executions 有权通过使用链接来定义执行顺序来调节多个执行路径中的直接存储器访问描述符的系统和方法公开(公告)号：US09164936B2
公开(公告)日：2015-10-20
申请号：US13731278
申请日：2012-12-31
Applicant: Silicon Laboratories Inc.
Inventor： Timothy E. Litch , Paul I. Zavalney
CPC classification number: G06F13/28
Abstract: An apparatus includes an integrated circuit that includes a processing core and a direct memory access (DMA) engine. The DMA engine is adapted to process descriptors to control DMA communications. The descriptors contain data indicating communication endpoints that are associated with the DMA communications. The DMA engine is adapted to use other data contained in at least one of the descriptors to control branching of descriptor execution among multiple execution paths.
Abstract translation: 一种装置包括集成电路，其包括处理核心和直接存储器存取（DMA）引擎。 DMA引擎适用于处理描述符以控制DMA通信。 描述符包含指示与DMA通信相关联的通信端点的数据。 DMA引擎适于使用包含在至少一个描述符中的其他数据来控制多个执行路径之间的描述符执行的分支。
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