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1.发明申请公开(公告)号：US20060115036A1
公开(公告)日：2006-06-01
申请号：US11333245
申请日：2006-01-18
IPC分类号： H03D3/24
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.
摘要翻译： 包括PLL电路的频率合成器装置的分数部分控制电路是用于控制与PLL电路的可变分频器分频的分数部分的多n-Δ级Δ-Σ调制器电路。 加法器将分数部分的数据与来自乘法器的输出数据相加，并将结果数据通过二阶积分器输出到量化器。 量化器用量化步长量化输入数据，并通过反馈电路将量化的数据输出到乘法器。 量化数据用作受控分数部分的数据。 乘法器将来自反馈电路的数据乘以量化步长，并将结果数据输出到加法器。 分数部分控制电路周期性地改变分数部分的数据，从而根据周期的平均值设置来自VCO的输出信号的频率。
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公开(公告)号：US20050271159A1
公开(公告)日：2005-12-08
申请号：US11080680
申请日：2005-03-16
CPC分类号： H03C3/0933 , H03C3/0925 , H04L27/12 , H04L27/2003
摘要： A frequency modulation apparatus 100 has a synthesizer 101, a differentiator 102 that differentiates phase modulation data and generates differential phase modulation data, an adder 103 that adds together that differential phase modulation data and carrier frequency data fractional part K and generates addition fractional part K1, an input data operation section 104 that receives addition fractional part K1 and carrier frequency data integer part M, generates integer part input data M1 and fractional part input data K2, and provides fractional part input data K2 to synthesizer 101, and an integer part data delay section 105 that delays integer part input data M1 before providing it to synthesizer 101. Input data operation section 104 makes M1=M−1 and K2=K1+1 when K1
摘要翻译： 频率调制装置100具有合成器101，微分器102，其对相位调制数据进行微分并产生差分相位调制数据;加法器103，将差分相位调制数据和载波频率数据小数部分K相加，生成加法分数部分K 1 ，接收加法分数部分K 1和载波频率数据整数部分M的输入数据操作部分104产生整数部分输入数据M 1和小数部分输入数据K 2，并向合成器101提供分数部分输入数据K 2，以及 整数部分数据延迟部分105，其在将整数部分输入数据M 1提供给合成器101之前将其延迟。 当K 1 <0时，输入数据运算部104使M 1 = M-1，K 2 = K 1 +1，当0 <= K 1 <1时，M 1 = M，K 2 = K 1，使M 1 = 1 + = 1，K 2 = K 1 -1。
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3.发明授权Fractional-N frequency synthesizer with multiple clocks having different timings 失效具有不同时序的多个时钟的分数N频率合成器公开(公告)号：US06728526B2
公开(公告)日：2004-04-27
申请号：US09794185
申请日：2001-02-26
申请人： Ryoichi Yamada , Shunsuke Hirano , Yasunori Miyahara , Hisashi Adachi , Hisashi Takahashi , Hiroki Kojima
发明人： Ryoichi Yamada , Shunsuke Hirano , Yasunori Miyahara , Hisashi Adachi , Hisashi Takahashi , Hiroki Kojima
IPC分类号： H04B106
CPC分类号： H03L7/1976
摘要： A frequency synthesizer device comprising a PLL circuit (9) and a frequency-division ratio control circuit (5). The PLL circuit (9) includes a phase comparator (1), a low-pass filter (2), a voltage-controlled oscillator (3), and a variable frequency divider (4). The frequency-division ratio control circuit (5) controls the variable frequency divider (4) such that a frequency division ratio of the variable frequency divider (4) is changed in time and a time average value of the frequency division ratio contains a value below a decimal point. Two different signals of an output signal fdiv of the variable frequency divider (4) and an output fdiv2 obtained via a delay element (10) are used as clocks of an accumulator portion (81) in the frequency-division ratio control circuit (5). The variation in the substrate potential and the variation in the power supply voltage generated by the operation of the frequency-division ratio control circuit (5) can be reduced, and the degradation of C/N of the frequency synthesizer can be suppressed.
摘要翻译： 一种频率合成器装置，包括PLL电路（9）和分频比控制电路（5）。 PLL电路（9）包括相位比较器（1），低通滤波器（2），压控振荡器（3）和可变分频器（4）。 分频比控制电路（5）控制可变分频器（4），使得可变分频器（4）的分频比在时间上变化，并且分频比的时间平均值包含低于 小数点。 使用分频比控制电路（5）中的可变分频器（4）的输出信号fdiv和通过延迟元件（10）获得的输出fdiv2的两个不同信号作为累加器部分（81）的时钟， 。 可以减小由分频比控制电路（5）的操作产生的基板电位的变化和电源电压的变化，并且可以抑制频率合成器的C / N的劣化。
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4.发明授权公开(公告)号：US07215215B2
公开(公告)日：2007-05-08
申请号：US11078703
申请日：2005-03-14
申请人： Shunsuke Hirano , Hisashi Adachi
发明人： Shunsuke Hirano , Hisashi Adachi
IPC分类号： H03C3/06
CPC分类号： H03C3/0983 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095
摘要： A phase modulation apparatus is provided whereby excellent RF phase modulation signals can be obtained even when the modulation sensitivity of a voltage controlled oscillator varies. Phase modulation apparatus 100 has: phase detector 105 that performs phase detection with respect to an RF phase modulation signal outputted from VCO 101; comparator 106 that compares the phase of the detected signal with the phase of a baseband phase modulation signal and outputs the difference between the signals; variable gain amplifier 107 that controls the gain of the baseband phase modulation signal based on the output of comparator 106 and supplies the gain-controlled baseband phase modulation signal to VCO 101. By this means, the signal level of the baseband phase modulation signal that is supplied to VCO 101 can be controlled in accordance with the modulation sensitivity of VCO 101, so that phase modulation apparatus 100 can be realized whereby excellent RF phase modulation signals even when the modulation sensitivity of VCO 101 varies.
摘要翻译： 提供一种相位调制装置，即使当压控振荡器的调制灵敏度变化时，也可以获得优异的RF相位调制信号。 相位调制装置100具有：相位检测器105，其相对于从VCO101输出的RF相位调制信号进行相位检测; 比较器106，其将检测信号的相位与基带相位调制信号的相位进行比较，并输出信号之间的差; 可变增益放大器107，其基于比较器106的输出来控制基带相位调制信号的增益，并将增益控制的基带相位调制信号提供给VCO101。 通过这种方式，可以根据VCO101的调制灵敏度来控制提供给VCO 101的基带相位调制信号的信号电平，从而可以实现相位调制装置100，从而即使在 VCO 101的调制灵敏度变化。
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公开(公告)号：US06717998B2
公开(公告)日：2004-04-06
申请号：US09733949
申请日：2000-12-12
IPC分类号： H03D324
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.
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公开(公告)号：US06441692B1
公开(公告)日：2002-08-27
申请号：US09154740
申请日：1998-09-17
申请人： Toshifumi Nakatani , Hisashi Adachi , Hiroaki Kosugi , Yuji Saito , Shunsuke Hirano , Hiroshi Haruki
发明人： Toshifumi Nakatani , Hisashi Adachi , Hiroaki Kosugi , Yuji Saito , Shunsuke Hirano , Hiroshi Haruki
IPC分类号： H03B2100
CPC分类号： H03L7/18 , H03L2207/10
摘要： The invention provides a high-speed PLL frequency synthesizer in which the frequency of a reference signal can be made larger than a frequency interval of an external output with a simple configuration. An n-th harmonic of an output of a voltage-controlled oscillator is caused to pass through a band pass filter. The frequency of an output of the band pass filter is divided by M in a variable frequency divider. The phase of an output of the variable frequency divider is compared with that of the reference signal in a phase comparator. An output of the phase comparator is smoothed by a loop filter. The output of the voltage-controlled oscillator is controlled by an output of the loop filter. The fundamental wave of the output of the voltage-controlled oscillator is caused to pass through another band pass filter, and then output to the outside. At this time, the frequency of the reference signal is n times a frequency interval of the fundamental wave of the output of the voltage-controlled oscillator.
摘要翻译： 本发明提供了一种高速PLL频率合成器，其中参考信号的频率可以被制成大于具有简单配置的外部输出的频率间隔。 使压控振荡器的输出的n次谐波通过带通滤波器。 带通滤波器的输出频率由可分频器M分频。 在相位比较器中，可变分频器的输出相位与参考信号的相位相比较。 相位比较器的输出由环路滤波器平滑。 压控振荡器的输出由环路滤波器的输出控制。 使压控振荡器的输出的基波通过另一个带通滤波器，然后输出到外部。 此时，参考信号的频率是压控振荡器的输出的基波的频率间隔的n倍。
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7.发明申请公开(公告)号：US20070013447A1
公开(公告)日：2007-01-18
申请号：US11410293
申请日：2006-04-25
申请人： Shunsuke Hirano , Hisashi Adachi
发明人： Shunsuke Hirano , Hisashi Adachi
IPC分类号： H03L7/00
CPC分类号： H04L27/20 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0966
摘要： There provides a two-point modulation phase modulation apparatus capable of obtaining an RF phase modulation signal of superior modulation precision with low power consumption and a simple configuration even in the event of inputting a wide band baseband modulation signal. A differentiator (21) of the opposite characteristics to the attenuation characteristics of anti-alias filter (22) is provided at the front stage of a D/A converter (6). As a result, it is possible to sufficiently suppress an alias signal without raising the sampling frequency of the D/A converter (6) (i.e. low power consumption) using an anti-alias filter (22) of a simple configuration (i.e. low cost) with a low order for a narrower bandwidth than a PLL modulation frequency bandwidth, and it is possible to obtain an RF phase modulation signal where the entire frequency band of input digital baseband modulation signal (S1) is reflected in a superior manner.
摘要翻译： 提供了即使在输入宽带基带调制信号的情况下，也能够获得具有低功耗的优良调制精度的RF相位调制信号和简单的配置的两点调制相位调制装置。 在D / A转换器（6）的前级设置有与抗混叠滤波器（22）的衰减特性相反特性的微分器（21）。 结果，可以使用简单配置的抗混叠滤波器（22）来充分抑制混叠信号而不提高D / A转换器（6）的采样频率（即，低功耗）（即，低成本 ）具有比PLL调制频率带宽更窄的带宽的低阶，并且可以获得输入数字基带调制信号（S1）的整个频带以优异的方式反映的RF相位调制信号。
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公开(公告)号：US07050525B2
公开(公告)日：2006-05-23
申请号：US10728863
申请日：2003-12-08
CPC分类号： H03L7/1976
摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.
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9.发明授权公开(公告)号：US07378918B2
公开(公告)日：2008-05-27
申请号：US11410293
申请日：2006-04-25
申请人： Shunsuke Hirano , Hisashi Adachi
发明人： Shunsuke Hirano , Hisashi Adachi
CPC分类号： H04L27/20 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0966
摘要： There provides a two-point modulation phase modulation apparatus capable of obtaining an RF phase modulation signal of superior modulation precision with low power consumption and a simple configuration even in the event of inputting a wide band baseband modulation signal. A differentiator (21) of the opposite characteristics to the attenuation characteristics of anti-alias filter (22) is provided at the front stage of a D/A converter (6). As a result, it is possible to sufficiently suppress an alias signal without raising the sampling frequency of the D/A converter (6) (i.e. low power consumption) using an anti-alias filter (22) of a simple configuration (i.e. low cost) with a low order for a narrower bandwidth than a PLL modulation frequency bandwidth, and it is possible to obtain an RF phase modulation signal where the entire frequency band of input digital baseband modulation signal (S1) is reflected in a superior manner.
摘要翻译： 提供了即使在输入宽带基带调制信号的情况下，也能够获得具有低功耗的优良调制精度的RF相位调制信号和简单的配置的两点调制相位调制装置。 在D / A转换器（6）的前级设置有与抗混叠滤波器（22）的衰减特性相反特性的微分器（21）。 结果，可以使用简单配置的抗混叠滤波器（22）来充分抑制混叠信号而不提高D / A转换器（6）的采样频率（即，低功耗）（即，低成本 ）具有比PLL调制频率带宽更窄的带宽的低阶，并且可以获得输入数字基带调制信号（S1）的整个频带以优异的方式反映的RF相位调制信号。
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公开(公告)号：US07199677B2
公开(公告)日：2007-04-03
申请号：US11080680
申请日：2005-03-16
IPC分类号： H03C3/06
CPC分类号： H03C3/0933 , H03C3/0925 , H04L27/12 , H04L27/2003
摘要： A frequency modulation apparatus 100 has a synthesizer 101, a differentiator 102 that differentiates phase modulation data and generates differential phase modulation data, an adder 103 that adds together that differential phase modulation data and carrier frequency data fractional part K and generates addition fractional part K1, an input data operation section 104 that receives addition fractional part K1 and carrier frequency data integer part M, generates integer part input data M1 and fractional part input data K2, and provides fractional part input data K2 to synthesizer 101, and an integer part data delay section 105 that delays integer part input data M1 before providing it to synthesizer 101. Input data operation section 104 makes M1=M−1 and K2=K1+1 when K1
摘要翻译： 频率调制装置100具有合成器101，微分器102，其对相位调制数据进行微分并产生差分相位调制数据;加法器103，将差分相位调制数据和载波频率数据小数部分K相加，生成加法分数部分K 1 ，接收加法分数部分K 1和载波频率数据整数部分M的输入数据操作部分104产生整数部分输入数据M 1和小数部分输入数据K 2，并向合成器101提供分数部分输入数据K 2，以及 整数部分数据延迟部分105，其在将整数部分输入数据M 1提供给合成器101之前将其延迟。 当K 1 <0时，输入数据运算部104使M 1 = M-1，K 2 = K 1 +1，当0 <= K 1 <1时，M 1 = M，K 2 = K 1，使M 1 = 1 + = 1，K 2 = K 1 -1。
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