公开(公告)号：US11720405B2

公开(公告)日：2023-08-08

申请号：US17145958

申请日：2021-01-11

申请人： Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

发明人： Wookeun Jung ,  Jaejin Lee ,  Seung Wook Lee

IPC分类号： G06F9/38 ,  G06N3/063 ,  G06F9/50 ,  G06F9/48 ,  G06F9/30

CPC分类号： G06F9/5027 ,  G06F9/30014 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/48 ,  G06N3/063

摘要： A processor-implemented accelerator method includes: reading, from a memory, an instruction to be executed in an accelerator; reading, from the memory, input data based on the instruction; and performing, on the input data and a parameter value included in the instruction, an inference task corresponding to the instruction.

公开(公告)号：US10725667B2

公开(公告)日：2020-07-28

申请号：US15874322

申请日：2018-01-18

申请人： SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

发明人： Jaejin Lee ,  Gangwon Jo

IPC分类号： G06F3/06 ,  G06F15/163 ,  G06F15/167 ,  G06F12/08 ,  G06F12/14

摘要： Disclosed herein are a method of transferring data in a parallel system including a main device and at least one accelerator, and a parallel system for performing the method. The method of transferring data in a heterogeneous system including a main device and at least one accelerator includes: turning off a write permission for a first main memory area corresponding to a first accelerator memory area where input data for a computation task is stored; performing the computation task by using the at least one accelerator; and turning off a read permission for a second main memory area corresponding to a second accelerator memory area where output data for the computation task is stored, in the state in which data of the second accelerator memory area has not been transferred to the second main memory area.

公开(公告)号：US09367291B2

公开(公告)日：2016-06-14

申请号：US14228868

申请日：2014-03-28

申请人： Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

发明人： Jin-Seok Lee ,  Seong-Gun Kim ,  Dong-Hoon Yoo ,  Seok-Joong Hwang ,  Jeongho Nah ,  Jaejin Lee ,  Jun Lee

IPC分类号： G06F9/45

CPC分类号： G06F8/40

摘要： An apparatus and method for generating vector code are provided. The apparatus and method generate vector code using scalar-type kernel code, without user's changing a code type or modifying data layout, thereby enhancing user's convenience of use and retaining the portability of OpenCL.

摘要翻译： 提供了一种用于产生矢量码的装置和方法。 该设备和方法使用标量型内核代码生成向量代码，无需用户更改代码类型或修改数据布局，从而提高用户使用方便性并保留OpenCL的可移植性。

公开(公告)号：US20240118878A1

公开(公告)日：2024-04-11

申请号：US18542544

申请日：2023-12-15

申请人： MOREH CORP. ,  Seoul National University R&DB Foundation

发明人： Jaejin Lee ,  Jungho Park ,  Gangwon Jo ,  Heehoon Kim ,  Jinpyo Kim

IPC分类号： G06F8/41 ,  G06N3/042

CPC分类号： G06F8/443 ,  G06N3/042

摘要： A method for determining optimization applicability on an intermediate representation from a program is performed by one or more processors, and includes receiving, as a query, a subgraph of the intermediate representation that is a subject of determination of optimization applicability, determining a validity of the query, and if the query is valid, determining optimization applicability on the subgraph, in which the program includes data and a plurality of operations, and the intermediate representation includes a plurality of data nodes, a plurality of operation nodes, and a plurality of edges representing input/output relationships between the plurality of data nodes and the plurality of operation nodes.

公开(公告)号：US20240118876A1

公开(公告)日：2024-04-11

申请号：US18542563

申请日：2023-12-15

申请人： MOREH CORP. ,  Seoul National University R&DB Foundation

发明人： Jaejin Lee ,  Jungho Park ,  Gangwon Jo ,  Heehoon KIM ,  Jinpyo KIM

IPC分类号： G06F8/41

CPC分类号： G06F8/41

摘要： A method for managing an intermediate representation from a program is executed by one or more processors, and includes extracting, from the program, information on data for input and output and information on operation, generating an intermediate representation from the program using the extracted information on data and the extracted information on operation, storing, in a database, a corresponding relationship between the program and the intermediate representation, storing execution information on operation of the intermediate representation, and deleting at least a part of the intermediate representation based on the execution information.

公开(公告)号：US09485303B2

公开(公告)日：2016-11-01

申请号：US13734407

申请日：2013-01-04

申请人： Seoul National University R&DB Foundation

发明人： Jaejin Lee ,  Jungwon Kim

IPC分类号： G06F15/177 ,  H04L29/08 ,  G06F9/54

CPC分类号： H04L67/10 ,  G06F9/545 ,  G06F9/547

摘要： A cluster system based on a parallel computing framework is provided, and the cluster system includes a host node configured to execute a host program for a parallel computing framework and a computing node configured to be connected to the host node and execute a kernel program for the parallel computing frame work.

摘要翻译： 提供了一种基于并行计算框架的集群系统，并且集群系统包括被配置为执行用于并行计算框架的主机程序的主机节点和被配置为连接到主机节点的计算节点，并执行用于 并行计算框架工作。

公开(公告)号：US09208088B2

公开(公告)日：2015-12-08

申请号：US13733396

申请日：2013-01-03

申请人： Seoul National University R&DB Foundation

发明人： Jaejin Lee ,  Junghyun Kim

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0815 ,  G06F12/0837 ,  G06F12/109 ,  G06F2212/656

摘要： A shared virtual memory management apparatus for ensuring cache coherence. When two or more cores request write permission to the same virtual memory page, the shared virtual memory management apparatus allocates a physical memory page for the cores to change data in the allocated physical memory page. Thereafter, changed data is updated in an original physical memory page, and accordingly it is feasible to achieve data coherence in a multi-core hardware environment that does not provide cache coherence.

摘要翻译： 一种用于确保高速缓存一致性的共享虚拟内存管理装置。 当两个或多个核心向相同的虚拟内存页面请求写入权限时，共享虚拟内存管理装置为核心分配物理存储器页面以改变所分配的物理存储器页面中的数据。 此后，在原始物理存储器页面中更新改变的数据，因此在不提供高速缓存一致性的多核硬件环境中实现数据一致性是可行的。