公开(公告)号：US20130140554A1

公开(公告)日：2013-06-06

申请号：US13686281

申请日：2012-11-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Yoshinori IEDA ,  Masaharu NAGAI

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/7869

Abstract: A semiconductor device including a minute transistor with a short channel length is provided. A gate insulating layer is formed over a gate electrode layer; an oxide semiconductor layer is formed over the gate insulating layer; a first conductive layer and a second conductive layer are formed over the oxide semiconductor layer; a conductive film is formed over the first conductive layer and the second conductive layer; a resist mask is formed over the conductive film by performing electron beam exposure; and then a third conductive layer and a fourth conductive layer are formed over and in contact with the first conductive layer and the second conductive layer, respectively, by selectively etching the conductive film.

公开(公告)号：US20150372123A1

公开(公告)日：2015-12-24

申请号：US14837565

申请日：2015-08-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Yoshinori IEDA ,  Masaharu NAGAI

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L29/66969 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/7869

Abstract: A semiconductor device including a minute transistor with a short channel length is provided. A gate insulating layer is formed over a gate electrode layer; an oxide semiconductor layer is formed over the gate insulating layer; a first conductive layer and a second conductive layer are formed over the oxide semiconductor layer; a conductive film is formed over the first conductive layer and the second conductive layer; a resist mask is formed over the conductive film by performing electron beam exposure; and then a third conductive layer and a fourth conductive layer are formed over and in contact with the first conductive layer and the second conductive layer, respectively, by selectively etching the conductive film.

Abstract translation: 提供了包括具有短沟道长度的微小晶体管的半导体器件。 在栅电极层上形成栅极绝缘层; 在栅绝缘层上形成氧化物半导体层; 在所述氧化物半导体层上形成第一导电层和第二导电层; 在第一导电层和第二导电层上形成导电膜; 通过进行电子束曝光在导电膜上形成抗蚀剂掩模; 然后通过选择性地蚀刻导电膜，分别在第一导电层和第二导电层上形成第三导电层和第四导电层，并与第二导电层接触。

公开(公告)号：US20170288064A1

公开(公告)日：2017-10-05

申请号：US15628699

申请日：2017-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo ITO ,  Daisuke MATSUBAYASHI ,  Masaharu NAGAI ,  Yoshiaki YAMAMOTO ,  Takashi HAMADA ,  Yutaka OKAZAKI ,  Shinya SASAGAWA ,  Motomu KURATA ,  Naoto YAMADE

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/46 ,  H01L29/66 ,  H01L21/425

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

公开(公告)号：US20140246694A1

公开(公告)日：2014-09-04

申请号：US14274143

申请日：2014-05-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kaoru Tsuchiya ,  Aya ANZAI ,  Masayuki SAKAKURA ,  Masaharu NAGAI ,  Yutaka MATSUDA

IPC: H01L33/52

CPC classification number: H01L33/52 ,  H01L27/3244 ,  H01L27/3276 ,  H01L51/5246 ,  H01L2251/5323 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object of the present invention is to provide such a sealing structure that a material to be a deterioration factor such as water or oxygen is prevented from entering from external and sufficient reliability is obtained in a display using an organic or inorganic electroluminescent element. In view of the above object, focusing on permeability of an interlayer insulating film, deterioration of an electroluminescent element is suppressed and sufficient reliability is obtained by preventing water entry from an interlayer insulating film according to the present invention.

Abstract translation: 本发明的目的是提供一种这样的密封结构，即在使用有机或无机电致发光元件的显示器中，可以获得防止外部和水中的劣化因素等水分或氧气的材料进入的可靠性的密封结构。 鉴于上述目的，着眼于层间绝缘膜的磁导率，抑制了电致发光元件的劣化，并且通过防止水从本发明的层间绝缘膜进入而获得足够的可靠性。

公开(公告)号：US20160372606A1

公开(公告)日：2016-12-22

申请号：US15182812

申请日：2016-06-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Daigo ITO ,  Daisuke MATSUBAYASHI ,  Masaharu NAGAI ,  Yoshiaki YAMAMOTO ,  Takashi HAMADA ,  Yutaka OKAZAKI ,  Shinya SASAGAWA ,  Motomu KURATA ,  Naoto YAMADE

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/425 ,  H01L21/46 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/78693 ,  H01L21/425 ,  H01L21/46 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7782 ,  H01L29/7854 ,  H01L29/7855 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

Abstract translation: 一种半导体器件包括：衬底上的第一绝缘层，第一绝缘层上的第一金属氧化物层，第一金属氧化物层上的氧化物半导体层，氧化物半导体层上的第二金属氧化物层， 第二金属氧化物层，第二金属氧化物层上的第二绝缘层，以及栅极绝缘层上的栅电极层。 栅极绝缘层包括与栅电极层的侧表面接触的区域。 第二绝缘层包括与栅极绝缘层接触的区域。 氧化物半导体层包括第一至第三区域。 第一区域包括与栅电极层重叠的区域。 位于第一和第三区域之间的第二区域包括与栅极绝缘层或第二绝缘层重叠的区域。 第二和第三区域各自包括含有元素N（N是磷，氩或氙）的区域。

公开(公告)号：US20200020835A1

公开(公告)日：2020-01-16

申请号：US16522202

申请日：2019-07-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kaoru TSUCHIYA ,  Aya ANZAI ,  Masayuki SAKAKURA ,  Masaharu NAGAI ,  Yutaka MATSUDA

IPC: H01L33/52 ,  H01L27/32 ,  H01L51/52

Abstract: An object of the present invention is to provide such a sealing structure that a material to be a deterioration factor such as water or oxygen is prevented from entering from external and sufficient reliability is obtained in a display using an organic or inorganic electroluminescent element. In view of the above object, focusing on permeability of an interlayer insulating film, deterioration of an electroluminescent element is suppressed and sufficient reliability is obtained by preventing water entry from an interlayer insulating film according to the present invention.