公开(公告)号：US10481668B2

公开(公告)日：2019-11-19

申请号：US15677050

申请日：2017-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Ook Song ,  Yun-Ju Kwon ,  Dong-Sik Cho ,  Byung-Tak Lee

IPC: G06F1/32 ,  G06F1/3225 ,  G06F15/78 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3234 ,  G11C5/14

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

公开(公告)号：US12271247B2

公开(公告)日：2025-04-08

申请号：US18500563

申请日：2023-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Ook Song ,  Yun-Ju Kwon ,  Dong-Sik Cho ,  Byung-Tak Lee

IPC: G06F1/32 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F15/78 ,  G11C5/14

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

公开(公告)号：US11836029B2

公开(公告)日：2023-12-05

申请号：US17827847

申请日：2022-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Ook Song ,  Yun-Ju Kwon ,  Dong-Sik Cho ,  Byung-Tak Lee

IPC: G06F1/32 ,  G11C5/14 ,  G06F1/3225 ,  G06F15/78 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3234

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G06F15/7821 ,  G11C5/14

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

公开(公告)号：US11347292B2

公开(公告)日：2022-05-31

申请号：US16670026

申请日：2019-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Ook Song ,  Yun-Ju Kwon ,  Dong-Sik Cho ,  Byung-Tak Lee

IPC: G06F1/32 ,  G06F1/3225 ,  G06F15/78 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3234 ,  G11C5/14

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

公开(公告)号：US09031161B2

公开(公告)日：2015-05-12

申请号：US14052033

申请日：2013-10-11

Applicant: Samsung Electronics Co. Ltd.

Inventor： Kyung-Chul Yoo ,  Bo-Rham Lee ,  Yun-Ju Kwon ,  Dong-Min Kim

IPC: H04L9/00 ,  H04L27/20 ,  H04L29/06 ,  H04L9/08 ,  H04L25/03 ,  H04L1/00 ,  H04L27/36

CPC classification number: H04L27/206 ,  H04L1/0003 ,  H04L1/0041 ,  H04L9/08 ,  H04L25/03866 ,  H04L27/2032 ,  H04L27/36 ,  H04L63/0428

Abstract: An apparatus for a transmit end in a wireless communication system is provided. The apparatus includes at least one scrambler configured to scramble a transmission bit stream, wherein the at least one scrambler comprises, a first circulation unit configured to output, during one cycle, at least one bit for scrambling odd-numbered bits of the transmission bit stream and at least one bit for scrambling even-numbered bits of the transmission bit stream, a second circulation unit configured to output, during one cycle, at least one bit for scrambling odd-numbered bits of the transmission bit stream and at least one bit for scrambling even-numbered bits of the transmission bit stream, and operators configured to generate a scrambled bit stream, wherein each of the operators generates a scrambled bit using an input bit, an output bit from the first circulation unit and an output bit from the second circulation unit.

Abstract translation: 提供了一种用于无线通信系统中的发送端的装置。 该装置包括至少一个扰码器，配置成对发送比特流进行加扰，其中至少一个扰频器包括：第一循环单元，被配置为在一个周期期间输出至少一个比特，用于对传输比特流进行加扰奇数比特 以及至少一个比特，用于对所述传输比特流的偶数位进行加扰;第二循环单元，被配置为在一个周期期间输出用于对所述传输比特流进行加扰奇数比特的至少一个比特，以及至少一个比特， 加扰传输比特流的偶数比特，以及被配置为生成加扰比特流的运算符，其中每个运算符使用输入比特生成加扰比特，来自第一循环单元的输出比特和来自第二循环单元的输出比特 循环单元