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    Dataflow accelerator architecture for general matrix-matrix multiplication and tensor computation in deep learning
    1.
    发明授权
    Dataflow accelerator architecture for general matrix-matrix multiplication and tensor computation in deep learning 有权

    公开(公告)号：US12164593B2

    公开(公告)日：2024-12-10

    申请号：US17374988

    申请日：2021-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Peng Gu ,  Krishna Malladi ,  Hongzhong Zheng ,  Dimin Niu

    IPC: G06F17/16 ,  G06F12/0802 ,  G06F12/0877 ,  G06N3/008 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08

    Abstract: A general matrix-matrix multiplication (GEMM) dataflow accelerator circuit is disclosed that includes a smart 3D stacking DRAM architecture. The accelerator circuit includes a memory bank, a peripheral lookup table stored in the memory bank, and a first vector buffer to store a first vector that is used as a row address into the lookup table. The circuit includes a second vector buffer to store a second vector that is used as a column address into the lookup table, and lookup table buffers to receive and store lookup table entries from the lookup table. The circuit further includes adders to sum the first product and a second product, and an output buffer to store the sum. The lookup table buffers determine a product of the first vector and the second vector without performing a multiply operation. The embodiments include a hierarchical lookup architecture to reduce latency. Accumulation results are propagated in a systolic manner.

    Database offloading engine
    5.
    发明授权
    Database offloading engine 有权

    公开(公告)号：US11334284B2

    公开(公告)日：2022-05-17

    申请号：US16195732

    申请日：2018-11-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Andrew Zhenwen Chang ,  Jongmin Gim ,  Hongzhong Zheng

    IPC: G06F3/06 ,  G06F21/62

    Abstract: A database offloading engine. In some embodiments, the database offloading engine includes a vectorized adder including a plurality of read-modify-write circuits, a plurality of sum buffers respectively connected to the read-modify-write circuits, a key address table, and a control circuit. The control circuit may be configured to receive a first key and a corresponding first value; to search the key address table for the first key; and, in response to finding, in the key address table, an address corresponding to the first key, to route the address and the first value to a read-modify-write circuit, of the plurality of read-modify-write circuits, corresponding to the address.

    HBM RAS cache architecture
    8.
    发明授权
    HBM RAS cache architecture 有权

    公开(公告)号：US11151006B2

    公开(公告)日：2021-10-19

    申请号：US16150239

    申请日：2018-10-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dimin Niu ,  Krishna Malladi ,  Hongzhong Zheng

    IPC: G06F11/00 ,  G06F11/20 ,  G06F3/06

    Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.

    PSEUDO MAIN MEMORY SYSTEM
    10.
    发明申请
    PSEUDO MAIN MEMORY SYSTEM 有权

    公开(公告)号：US20210271594A1

    公开(公告)日：2021-09-02

    申请号：US17322805

    申请日：2021-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. Malladi ,  Jongmin Gim ,  Hongzhong Zheng

    IPC: G06F12/02 ,  G06F13/16

    Abstract: A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.

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