公开(公告)号：US20140008789A1

公开(公告)日：2014-01-09

申请号：US13889343

申请日：2013-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae CHO

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/49822 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/92242 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161

Abstract: Provided are a semiconductor package, a semiconductor device provided with the same, and a method of fabricating the same. The semiconductor package may include a package substrate including a central region and a peripheral region, a first semiconductor chip provided on the package substrate, a first connection pattern provided on the central region of the package substrate to connect the package substrate electrically to the first semiconductor chip, at least one second semiconductor chip provided on the peripheral region of the package substrate and between the package substrate and the first semiconductor chip, and a second connection pattern provided on the peripheral region of the package substrate to connect the first semiconductor chip electrically to the second semiconductor chip.

Abstract translation: 提供一种半导体封装，具备该半导体封装的半导体器件及其制造方法。 半导体封装可以包括包括中心区域和外围区域的封装衬底，设置在封装衬底上的第一半导体芯片，设置在封装衬底的中心区域上的第一连接图案，以将封装衬底电连接到第一半导体 芯片，设置在封装基板的周边区域和封装基板与第一半导体芯片之间的至少一个第二半导体芯片，以及设置在封装基板的外围区域上的第二连接图案，以将第一半导体芯片电连接到 第二个半导体芯片。

公开(公告)号：US20190355671A1

公开(公告)日：2019-11-21

申请号：US16530993

申请日：2019-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae CHO ,  Sundae KIM ,  HYUNGGIL BAEK ,  Namgyu BAEK ,  Seunghun SHIN ,  Donghoon WON

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/58 ,  H01L21/02

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

公开(公告)号：US20160086921A1

公开(公告)日：2016-03-24

申请号：US14732660

申请日：2015-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae CHO

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/4012 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2224/05554 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06135 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/92163 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: A semiconductor package that includes a package substrate, a lower semiconductor chip mounted on the package substrate, and an upper semiconductor chip stacked on the lower semiconductor chip in a cascade shape is provided. An active surface of the lower semiconductor chip is facing an active surface of the upper semiconductor chip.

Abstract translation: 提供一种半导体封装，其包括封装基板，安装在封装基板上的下部半导体芯片和层叠在下部半导体芯片上的上部半导体芯片。 下半导体芯片的有源表面面向上半导体芯片的有源表面。

公开(公告)号：US20250149480A1

公开(公告)日：2025-05-08

申请号：US18804574

申请日：2024-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhee LEE ,  Yun-Rae CHO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package includes: a first semiconductor chip; and a second semiconductor chip connected to the first semiconductor chip, wherein the first semiconductor chip includes: a first semiconductor layer; a first through electrode penetrating the first semiconductor layer; and a first connection pad part positioned on the first semiconductor layer and including a plurality of first connection pads connected to the first through electrode, wherein the second semiconductor chip includes: a second semiconductor layer; a second through electrode penetrating the second semiconductor layer; and a second connection pad part positioned on the second semiconductor layer to face the first connection pad part and including a plurality of second connection pads connected to the second through electrode, wherein the plurality of first connection pads is in contact with the plurality of second connection pads, respectively.

公开(公告)号：US20190295997A1

公开(公告)日：2019-09-26

申请号：US16437595

申请日：2019-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun-Rae CHO

IPC: H01L25/10 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31

Abstract: A semiconductor device includes a package substrate, a semiconductor chip on a first region of the package substrate, and a solder bump on a second region of the package substrate. The solder bump includes a core portion and a peripheral portion encapsulating the core portion. The peripheral portion includes a first segment with a first melting point and a second segment with a second melting point that is less than the first melting point.

公开(公告)号：US20180261555A1

公开(公告)日：2018-09-13

申请号：US15850336

申请日：2017-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae CHO ,  Sundae KIM ,  Hyunggil Baek ,  Namgyu BAEK ,  Seunghun SHIN ,  Donghoon WON

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/02

Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

公开(公告)号：US20170294360A1

公开(公告)日：2017-10-12

申请号：US15630934

申请日：2017-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sundae KIM ,  Yun-Rae CHO ,  Namgyu BAEK ,  Seokhyun LEE

IPC: H01L21/66 ,  H01L21/768

CPC classification number: H01L22/32 ,  H01L21/76877 ,  H01L21/822 ,  H01L22/14 ,  H01L22/34 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10897

Abstract: Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.

公开(公告)号：US20160233171A1

公开(公告)日：2016-08-11

申请号：US14985379

申请日：2015-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sundae KIM ,  Yun-Rae CHO ,  Namgyu BAEK ,  Seokhyun LEE

IPC: H01L23/544

CPC classification number: H01L22/32 ,  H01L21/76877 ,  H01L21/822 ,  H01L22/14 ,  H01L22/34 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10897

Abstract: Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line sequentially stacked on the substrate, and a defect detection structure provided on a peripheral region of the substrate to include first and second defect detection lines provided at the same levels as those of the first and second lines, respectively.

Abstract translation: 本发明提供一种半导体器件，其包括设置在基板的单元区域上的互连结构，包括依次层叠在基板上的第一线和第二线，以及设置在基板的周边区域上的缺陷检测结构，包括第一和第二 缺陷检测线分别与第一和第二线的级别相同。