公开(公告)号：US20160372423A1

公开(公告)日：2016-12-22

申请号：US15156327

申请日：2016-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mi-Na CHOI ,  Young-Deuk KIM ,  Jae-Choon KIM ,  Eon-Soo JANG ,  Hee-Jung HWANG

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/45099

Abstract: A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of mount regions in which semiconductor chips may be mounted, and a peripheral region. The internal circuits may be arranged in the mount regions. The warpage-suppressing member is different from the semiconductor chips and may be arranged in at least one of the mount regions to suppress a warpage of the insulating substrate. Thus, warpage of the package substrate may be suppressed during a reflow process.

Abstract translation: 封装基板可以包括绝缘基板，内部电路和翘曲抑制部件。 绝缘基板可以具有可以安装半导体芯片的多个安装区域和周边区域。 内部电路可以布置在安装区域中。 翘曲抑制部件与半导体芯片不同，并且可以布置在至少一个安装区域中，以抑制绝缘基板的翘曲。 因此，可以在回流工艺期间抑制封装衬底的翘曲。

公开(公告)号：US20250062257A1

公开(公告)日：2025-02-20

申请号：US18435016

申请日：2024-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Deuk KIM ,  Heejung HWANG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/48 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor chip including a body that having a front surface and a rear surface; a wiring structure above the front surface of the body; a through via penetrating the body, and the through via is connected to the wiring structure; a heat dissipation structure above the rear surface of the body, and the heat dissipation structure includes a conductive layer connected to the through via; and a signal pad and a heat dissipation pad on the heat dissipation structure, and the signal pad and the heat dissipation pad are connected to the conductive layer.

公开(公告)号：US20190198489A1

公开(公告)日：2019-06-27

申请号：US16162598

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Choon KIM ,  Young-Deuk KIM ,  Woo-Hyun PARK

IPC: H01L25/18 ,  H05K1/18 ,  H01L23/427

Abstract: An electronic device includes a substrate, a first electronic product arranged on the substrate, a second electronic product arranged on the substrate to be spaced apart from the first electronic product, and a heat dissipating assembly covering the first and second electronic products, the heat dissipating assembly comprising a heat dissipating chamber including a hermetically sealed space having a first portion having one or more gaps in which a flowable heat dissipation fluid is disposed and having a second portion in which a solid thermal conductive member is disposed to prevent the flow of the heat dissipation fluid across the second portion with respect to a plan view, wherein the first portion of the heat dissipating chamber has a first thermal conductivity and overlaps with the first electronic product in the plan view, wherein the solid thermal conductive member has a second thermal conductivity less than the first thermal conductivity, wherein the solid thermal conductive member overlaps with the second electronic product in the plan view, wherein the overlapping area of the solid thermal conductive member with the second electronic product is greater than 50% of an area of the second electronic product in the plan view.

公开(公告)号：US20140167245A1

公开(公告)日：2014-06-19

申请号：US14106912

申请日：2013-12-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Deuk KIM ,  Ji-Chul KIM

IPC: H01L23/36

CPC classification number: H01L23/36 ,  H01L21/563 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/49894 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A semiconductor package includes a flexible base film having a first surface opposing a second surface, a semiconductor chip mounted on the first surface of the base film, and a touch sensing structure including at least one conductive pattern adjacent to the semiconductor chip. The at least one conductive pattern is disposed through the base film and has a surface exposed at the second surface of the base film. A contact condition of the semiconductor package is determined based on detection of a conductive path between the at least one conductive pattern and a conductive frame or support surface of the semiconductor package. The contact condition provides an indication of heat dissipation that may be expected to occur for the chip during operation.

Abstract translation: 半导体封装包括具有与第二表面相对的第一表面的柔性基膜，安装在基膜的第一表面上的半导体芯片，以及包括与半导体芯片相邻的至少一个导电图案的触摸感测结构。 所述至少一个导电图案设置穿过所述基底膜并具有在所述基底膜的第二表面处露出的表面。 基于对至少一个导电图案和半导体封装的导电框架或支撑表面之间的导电路径的检测来确定半导体封装的接触状态。 接触条件提供可能预期在操作期间芯片发生的散热的指示。