公开(公告)号：US20250151272A1

公开(公告)日：2025-05-08

申请号：US18746736

申请日：2024-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joon MOON ,  Young Hwan SON ,  Shin Hwan KANG ,  Suk Kang SUNG

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B43/35 ,  H10B80/00

Abstract: Semiconductor memory devices including memory cells arranged three-dimensionally, methods for fabricating the same, and electronic systems including the same are provided. The semiconductor memory device includes a first stacked structure including first gate electrodes sequentially stacked and spaced apart from each other, a second stacked structure on the first stacked structure and including second gate electrodes sequentially stacked and spaced apart from each other, and a channel structure extending in a vertical direction and passing through the first and second stacked structures, wherein the channel structure includes a channel layer including a first pillar portion crossing the first gate electrodes, a second pillar portion crossing the second gate electrodes, and a horizontal portion extending along a plane crossing the vertical direction, the horizontal portion connecting the first and second pillar portions, and a data storage layer extending along an outer side of the channel layer.

公开(公告)号：US20200027894A1

公开(公告)日：2020-01-23

申请号：US16262100

申请日：2019-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Hwan SON ,  Seo Goo KANG ,  Shin Hwan KANG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  G11C16/04

Abstract: A three-dimensional semiconductor memory device includes: gate electrodes and mold insulation layers alternately stacked on a substrate; a channel layer passing through the gate electrodes and the mold insulation layers; and a gate dielectric layer between the gate electrodes and the channel layer. The gate dielectric layer and the channel layer may be in an upper portion of the substrate and may be bent at a first angle and extend under the mold insulation layers in the upper portion of the substrate.

公开(公告)号：US20200381449A1

公开(公告)日：2020-12-03

申请号：US16718498

申请日：2019-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je Suk MOON ,  Seo-Goo KANG ,  Young Hwan SON ,  Kohji KANAMORI ,  Jee Hoon HAN

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A nonvolatile memory device includes a mold structure having a stack of word lines on a substrate and first and second string selection lines on the word lines, a first cutting structure through the mold structure, a second cutting structure through the mold structure, the second cutting structure being spaced apart from the first cutting structure, a channel structure penetrating the mold structure to be connected to the substrate, the channel structure being between the first and second cutting structures, a first cutting line cutting through the first string selection line but not through the second string selection line, the first cutting line being between the first and second cutting structures, and a second cutting line cutting through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.

公开(公告)号：US20230189525A1

公开(公告)日：2023-06-15

申请号：US18104328

申请日：2023-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Joon RYU ,  Young Hwan SON ,  Seo-Goo KANG ,  Jung Hoon JUN ,  Kohji KANAMORI ,  Jee Hoon HAN

IPC: H10B43/27 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.

公开(公告)号：US20220139957A1

公开(公告)日：2022-05-05

申请号：US17579656

申请日：2022-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je Suk MOON ,  Seo-Goo KANG ,  Young Hwan SON ,  Kohji KANAMORI ,  Jee Hoon HAN

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A nonvolatile memory device includes a mold structure having a stack of word lines on a substrate and first and second string selection lines on the word lines, a first cutting structure through the mold structure, a second cutting structure through the mold structure, the second cutting structure being spaced apart from the first cutting structure, a channel structure penetrating the mold structure to be connected to the substrate, the channel structure being between the first and second cutting structures, a first cutting line cutting through the first string selection line but not through the second string selection line, the first cutting line being between the first and second cutting structures, and a second cutting line cutting through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.

公开(公告)号：US20210313344A1

公开(公告)日：2021-10-07

申请号：US17101401

申请日：2020-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Joon RYU ,  Young Hwan SON ,  Seo-Goo KANG ,  Jung Hoon JUN ,  Kohji KANAMORI ,  Jee Hoon HAN

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.