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    METHODS OF FABRICATING SEMICONDUCTOR DEVICES
    1.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250118600A1

    公开(公告)日：2025-04-10

    申请号：US18984957

    申请日：2024-12-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Uihyoung Lee ,  Honyun Park ,  Jongseok Lee ,  Sewan Kim ,  Taesung Lee

    IPC: H01L21/768 ,  C23C14/04

    Abstract: A method of fabricating a semiconductor device includes forming a dielectric layer on a lower structure. The method includes forming an opening to penetrate through the dielectric layer. The method includes alternately repeating a first operation, in which a first sputtering deposition process is performed to form a first metal pattern in the opening, and a second operation, in which a second sputtering deposition process is performed to form a second metal pattern in the opening, two or more times to form a first metal layer. The method includes forming a second metal layer on the first metal layer in an electroplating manner, and planarizing the first and second metal layers. Moreover, first and second process times, during which the first sputtering deposition process and the second sputtering deposition process, respectively, are performed, are each about five seconds or less.

    Methods of fabricating semiconductor devices
    4.
    发明授权
    Methods of fabricating semiconductor devices 有权

    公开(公告)号：US12211745B2

    公开(公告)日：2025-01-28

    申请号：US17558699

    申请日：2021-12-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Uihyoung Lee ,  Honyun Park ,  Jongseok Lee ,  Sewan Kim ,  Taesung Lee

    IPC: H01L21/768 ,  H01L21/285

    Abstract: A method of fabricating a semiconductor device includes forming a dielectric layer on a lower structure. The method includes forming an opening to penetrate through the dielectric layer. The method includes alternately repeating a first operation, in which a first sputtering deposition process is performed to form a first metal pattern in the opening, and a second operation, in which a second sputtering deposition process is performed to form a second metal pattern in the opening, two or more times to form a first metal layer. The method includes forming a second metal layer on the first metal layer in an electroplating manner, and planarizing the first and second metal layers. Moreover, first and second process times, during which the first sputtering deposition process and the second sputtering deposition process, respectively, are performed, are each about five seconds or less.

    SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT
    5.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT 有权

    公开(公告)号：US20210320664A1

    公开(公告)日：2021-10-14

    申请号：US17077891

    申请日：2020-10-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

    IPC: H03L7/081 ,  G11C7/22 ,  H03K5/133 ,  H03L7/085

    Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

    SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT
    8.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DELAY COMPENSATION CIRCUIT 有权

    公开(公告)号：US20230091026A1

    公开(公告)日：2023-03-23

    申请号：US17994296

    申请日：2022-11-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Anil Kavala ,  Seonkyoo Lee ,  Taesung Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

    IPC: H03L7/081 ,  H03L7/085 ,  H03K5/133 ,  G11C7/22

    Abstract: A semiconductor device includes an internal clock generation circuit configured to generate an internal clock; a plurality of unit circuits configured to have a first unit circuit and a second unit circuit operating while being synchronized with an internal clock; a plurality of transfer circuits including a first transfer circuit configured to provide a first transfer path having a first delay time, and a second transfer circuit configured to provide a second transfer path having a second delay time different from the first delay time; and a delay compensation circuit configured to compare a first clock input to the first unit circuit through the first transfer path with a second clock input to the second unit circuit through the second transfer path, and to adjust the second delay time so that the adjusted second delay time matches the first delay time.

    METHODS OF FABRICATING SEMICONDUCTOR DEVICES
    9.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220359282A1

    公开(公告)日：2022-11-10

    申请号：US17558699

    申请日：2021-12-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Uihyoung Lee ,  Honyun Park ,  Jongseok Lee ,  Sewan Kim ,  Taesung Lee

    IPC: H01L21/768 ,  H01L21/285

    Abstract: A method of fabricating a semiconductor device includes forming a dielectric layer on a lower structure. The method includes forming an opening to penetrate through the dielectric layer. The method includes alternately repeating a first operation, in which a first sputtering deposition process is performed to form a first metal pattern in the opening, and a second operation, in which a second sputtering deposition process is performed to form a second metal pattern in the opening, two or more times to form a first metal layer. The method includes forming a second metal layer on the first metal layer in an electroplating manner, and planarizing the first and second metal layers. Moreover, first and second process times, during which the first sputtering deposition process and the second sputtering deposition process, respectively, are performed, are each about five seconds or less.

    Data training method of storage device
    10.
    发明授权
    Data training method of storage device 有权

    公开(公告)号：US10366022B2

    公开(公告)日：2019-07-30

    申请号：US15871637

    申请日：2018-01-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chulseung Lee ,  Taesung Lee ,  Choongeui Lee ,  Soon Suk Hwang

    IPC: G06F13/16 ,  G06K9/62 ,  G06F13/12 ,  G06N20/00

    Abstract: A data training method of a storage device, which includes a storage controller and a nonvolatile memory device, includes transmitting a read training command to the nonvolatile memory device, receiving a first training pattern output from the nonvolatile memory device in response to the read training command, receiving a second training pattern output from the nonvolatile memory device in response to the read training command, comparing the received first training pattern and the received second training pattern with a reference pattern, and determining a read timing offset of the storage controller depending on the comparison result.

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