公开(公告)号：US20210027837A1

公开(公告)日：2021-01-28

申请号：US16803450

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryul Kim ,  Taehui NA ,  Dueung KIM ,  Jongmin BAEK

IPC: G11C11/56 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074

Abstract: The memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row control circuit including a plurality of row switches corresponding to the word lines, a column control circuit including a plurality of column switches corresponding to the bit lines, and a control logic circuit configured to control pre-charge operations on a word line and a bit line of a selected memory cell and perform a control operation to float the word line and the bit line together after a pre-charge period during a data reading operation. One of the word line and the bit line is floated after the pre-charge period and the other one is pseudo-floated after the pre-charge period.

公开(公告)号：US20210090651A1

公开(公告)日：2021-03-25

申请号：US16999189

申请日：2020-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryul KIM ,  Jinyoung KIM ,  Taehui NA

IPC: G11C13/00 ,  G11C11/56

Abstract: A memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells disposed in an area where a plurality of word lines and a plurality of bit lines cross each other; a row decoder including row switches and configured to perform a selection operation on the plurality of word lines; a column decoder including column switches and configured to perform a selection operation on the plurality of bit lines; and a control logic configured to control, in a data read operation, a precharge operation to be performed on a selected word line in a word line precharge period, and to control a precharge operation to be performed on a selected bit line in a bit line precharge period; wherein a row switch connected to the selected word line is weakly turned on in the bit line precharge period.

公开(公告)号：US20200234736A1

公开(公告)日：2020-07-23

申请号：US16560127

申请日：2019-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Rie SIM ,  Taehui NA

IPC: G11C5/06 ,  H01L27/24 ,  H01L45/00 ,  G11C5/02

Abstract: A variable resistance memory device includes memory cell stacks arranged in a first direction, the memory cell stacks including a first memory cell stack and a second memory cell stack. Each of the memory cell stacks includes a plurality of word lines, each word line of the plurality of word lines extending in a second direction intersecting the first direction and arranged in a third direction intersecting the first and second directions, and a memory cell connected to each of the plurality of word lines. Each of the memory cells includes a switching element and a variable resistance element. Each of the plurality of word lines of the first memory cell stack have a first thickness, in the first direction, of first word lines of the first memory cell stack is less than a second thickness, in the first direction, of each of the plurality of word lines of the second memory cell stack.