公开(公告)号：US20210027837A1

公开(公告)日：2021-01-28

申请号：US16803450

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryul Kim ,  Taehui NA ,  Dueung KIM ,  Jongmin BAEK

IPC: G11C11/56 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074

Abstract: The memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row control circuit including a plurality of row switches corresponding to the word lines, a column control circuit including a plurality of column switches corresponding to the bit lines, and a control logic circuit configured to control pre-charge operations on a word line and a bit line of a selected memory cell and perform a control operation to float the word line and the bit line together after a pre-charge period during a data reading operation. One of the word line and the bit line is floated after the pre-charge period and the other one is pseudo-floated after the pre-charge period.