Abstract:
A binary complementary metal-oxide-semiconductor (CMOS) image sensor includes a pixel array and a readout circuit. The pixel array includes at least one pixel having a plurality of sub-pixels. The readout circuit is configured to quantize a pixel signal output from the pixel using a reference signal. The pixel signal corresponds to sub-pixel signals output from sub-pixels, from among the plurality of sub-pixels, activated in response to incident light.
Abstract:
The present invention relates to a 5th-generation (5G) or pre-5G communication system which is provided for supporting a higher data transfer rate after a 4th-generation (4G) communication system such as a long term evolution (LTE). The present invention provides a method for selecting, by an access point (AP), a beam in a communication system supporting a beamforming scheme, the method comprising: a step of transmitting information which indicates whether or not a duplicated beacon transmission interval (BTI) is operated; and a step of performing a transmit sector sweep (TXSS) process at least twice during the duplicated BTI.
Abstract:
A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.
Abstract:
A stack type image sensor may include: a first chip including a via isolation trench penetrating a first substrate, a via isolation layer including an insulation material in the via isolation trench, a first conductive layer on the first substrate, and a first insulation layer; a second chip including a second conductive layer on a second substrate, and a second insulation layer contacting the first insulation layer; a first via trench penetrating the first substrate to expose the second conductive layer with respect to the trench; and a first through via formed in the first via trench, and including a third conductive layer insulated from the first substrate by the via isolation layer, the third conductive layer electrically connecting the first conductive layer to the second conductive layer. The third conductive layer may be formed in the via isolation trench.
Abstract:
An image sensor is provided. The image sensor includes a well of a second conductivity type formed on an impurity layer of a first conductivity type, source and drain regions of the first conductivity type, formed in the well to be spaced apart from each other, a first photo diode of the first conductivity type formed in the well to overlap the source and drain regions, a second photo diode of the first conductivity type formed so as not to overlap the source and drain regions and formed to be adjacent to the first photo diode, and a gate electrode formed on the first and second photo diodes.