公开(公告)号：US20210066145A1

公开(公告)日：2021-03-04

申请号：US17006186

申请日：2020-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEHYO KIM ,  CHANHO KIM ,  DAESEOK BYEON

IPC: H01L21/66 ,  H01L23/00 ,  H01L27/11573

Abstract: A nonvolatile memory device includes a memory cell region including first pads and a peripheral circuit region including second pads. The regions comprises switches that are electrically connected with the pads, respectively, a test signal generator that generates test signals and to transmit the test signals to the switches, internal circuits that receive first signals through the pads and the switches, to perform operations based on the first signals, and to output second signals through the switches and the pads based on a result of the operations, and a switch controller that controls the switches so that the pads communicate with the test signal generator during a test operation and that the pads communicate with the internal circuits after a completion of the test operation. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

公开(公告)号：US20210124693A1

公开(公告)日：2021-04-29

申请号：US16865580

申请日：2020-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEHYO KIM ,  DAESEOK BYEON ,  TAEHONG KWON ,  CHANHO KIM ,  TAEYUN LEE

IPC: G06F12/123 ,  G06F12/02 ,  G06F12/14 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4091

Abstract: A memory device includes; a memory area including a first memory area including first memory cells storing N-bit data and a second memory area including second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

公开(公告)号：US20210124679A1

公开(公告)日：2021-04-29

申请号：US17007501

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEHYO KIM ,  DAESEOK BYEON ,  TAEHONG KWON ,  CHANHO KIM ,  TAEYUN LEE

IPC: G06F12/02 ,  G06F12/123 ,  G06F12/0811 ,  G06F12/14 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/4091

Abstract: A memory device comprises a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, wherein the memory cell region includes a first memory area having first memory cells storing N-bit data and a second memory area having second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and the peripheral circuit region includes a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

公开(公告)号：US20210066171A1

公开(公告)日：2021-03-04

申请号：US16827746

申请日：2020-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEHYO KIM ,  CHANHO KIM ,  DAESEOK BYEON

IPC: H01L23/495 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor die includes first pads, switches that are electrically connected with the first pads, respectively, a test signal generator that generates test signals and to transmit the test signals to the switches, internal circuits that receive first signals through the first pads and the switches, to perform operations based on the first signals, and to output second signals through the switches and the first pads based on a result of the operations, and a switch controller that controls the switches so that the first pads communicate with the test signal generator during a test operation and that the first pads communicate with the internal circuits after a completion of the test operation.