公开(公告)号：US11004732B2

公开(公告)日：2021-05-11

申请号：US16454860

申请日：2019-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-ki Min ,  Koung-min Ryu ,  Sung-soo Kim ,  Sang-koo Kang

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234

Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively; forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region; forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including first colloid; and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.

公开(公告)号：US10381265B2

公开(公告)日：2019-08-13

申请号：US15589169

申请日：2017-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-ki Min ,  Koung-min Ryu ,  Sung-soo Kim ,  Sang-koo Kang

IPC: H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively, forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region, forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including a first colloid, and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.

公开(公告)号：US10256318B2

公开(公告)日：2019-04-09

申请号：US15404659

申请日：2017-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-ho Jeon ,  Dae-hyun Jang ,  Seung-seok Ha ,  Young-ju Park ,  Sun-ki Min

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/321 ,  H01L21/8234

Abstract: A method of manufacturing a semiconductor device includes forming dummy gate structures including a dummy gate insulating layer and dummy gate electrodes, on a first region of a semiconductor substrate, the first region including a patterning region, forming spacers on two side walls of each of the dummy gate structures, forming an interlayer insulating layer on the semiconductor substrate and the dummy gate structures, forming a protective insulating layer on a second region of the semiconductor substrate, the second region including a non-patterning region, forming a liner layer on the protective insulating layer, planarizing the interlayer insulating layer by using the liner layer as an etching mask to expose top surfaces of the dummy gate structures, forming openings by removing the dummy gate structures to expose the semiconductor substrate between the spacers, and forming gate structures including a gate insulating layer and metal gate electrodes, in the openings.

公开(公告)号：US20190318961A1

公开(公告)日：2019-10-17

申请号：US16454860

申请日：2019-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-ki Min ,  Koung-min Ryu ,  Sung-soo Kim ,  Sang-koo Kang

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/423

Abstract: A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively, forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region, forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including a first colloid, and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.

公开(公告)号：US20170309724A1

公开(公告)日：2017-10-26

申请号：US15404659

申请日：2017-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-ho JEON ,  Dae-hyun JANG ,  Seung-seok HA ,  Young-ju Park ,  Sun-ki Min

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device includes forming dummy gate structures including a dummy gate insulating layer and dummy gate electrodes, on a first region of a semiconductor substrate, the first region including a patterning region, forming spacers on two side walls of each of the dummy gate structures, forming an interlayer insulating layer on the semiconductor substrate and the dummy gate structures, forming a protective insulating layer on a second region of the semiconductor substrate, the second region including a non-patterning region, forming a liner layer on the protective insulating layer, planarizing the interlayer insulating layer by using the liner layer as an etching mask to expose top surfaces of the dummy gate structures, forming openings by removing the dummy gate structures to expose the semiconductor substrate between the spacers, and forming gate structures including a gate insulating layer and metal gate electrodes, in the openings.