公开(公告)号：US20230328988A1

公开(公告)日：2023-10-12

申请号：US18166854

申请日：2023-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil KIM ,  Siyeong YANG

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A vertical semiconductor device may include a substrate, a pattern structure on the substrate, and a channel structure in a channel hole passing through the pattern structure. The pattern structure may include insulation patterns and gate structures alternately stacked in a vertical direction perpendicular to an upper surface of the substrate. The channel structure may extend in the vertical direction. The channel structure may include a data storage structure on an inner surface of the channel hole, a channel contacting the data storage structure, a lower pattern on the channel positioned at a lower portion of the channel hole, and a filling insulation pattern on the channel and the lower pattern. The channel may have a cylindrical shape. The lower pattern may include an oxide including silicon and germanium.

公开(公告)号：US20240397716A1

公开(公告)日：2024-11-28

申请号：US18644739

申请日：2024-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siyeong YANG ,  Yuyeon KIM ,  Chaeho KIM

IPC: H10B43/27 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a peripheral circuit structure including a plurality of circuits, and a cell array structure overlapping the peripheral circuit structure in a vertical direction. The cell array structure includes a common source line, a stack structure including a plurality of gate layers and a plurality of interlayer insulating layers which are alternately stacked on the common source line, and a plurality of channel structures in channel holes penetrating a memory cell area of the stack structure and connected to the common source line. Each of the plurality of channel structures includes a channel layer including an upper channel layer and a lower channel layer each having a single-crystal structure, and a crystal orientation of the upper channel layer is different from a crystal orientation of the lower channel layer.

公开(公告)号：US20230292509A1

公开(公告)日：2023-09-14

申请号：US18072276

申请日：2022-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Siyeong YANG ,  Yuyeon KIM ,  Woosung LEE

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/10 ,  H01L23/528 ,  H10B41/35 ,  H10B43/35 ,  H10B43/10

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11565

Abstract: A method of manufacturing a semiconductor device includes forming a molded structure by stacking interlayer insulating layers alternately with sacrificial layers on a plate layer, forming channel holes passing through the molded structure, forming channel layers doped with non-conductive impurities in the channel holes, forming a metal layer above the channel holes, forming metal silicide layers on upper ends of the channel layers using the metal layer, crystallizing the channel layers using the metal silicide layers by performing a heat treatment process at a temperature of 800 degrees or more, forming openings penetrating through the molded structure and extending in one direction, removing the sacrificial layers exposed through the openings, and forming gate electrodes, by filling regions from which the sacrificial layers have been removed, with a conductive material. After the crystallizing, the metal silicide layers are located lower than a lowermost gate electrode among the gate electrodes.

公开(公告)号：US20230269943A1

公开(公告)日：2023-08-24

申请号：US18166237

申请日：2023-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siyeong YANG ,  Yuyeon Kim ,  Minjun Oh

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure in which a plurality of interlayer insulating layers and a plurality of sacrificial layers are alternately stacked on a substrate, etching the stacked structure to form an opening exposing a part of the substrate through the stacked structure, forming a channel layer on a part of the substrate. The forming of the channel layer includes forming a first amorphous silicon layer at a first temperature on the part of the substrate by supplying a silicon source gas and an impurity source gas together and forming a second amorphous silicon layer at a second temperature on the first amorphous silicon layer by supplying the silicon source gas and not supplying the impurity source gas after the forming of the first amorphous silicon layer, and the second temperature is higher than the first temperature.