公开(公告)号：US20240257851A1

公开(公告)日：2024-08-01

申请号：US18499551

申请日：2023-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon CHA ,  Yuhwan RO ,  Seungwoo SEO

IPC: G11C8/06 ,  G11C7/10 ,  G11C8/04

CPC classification number: G11C8/06 ,  G11C7/1063 ,  G11C8/04

Abstract: A memory device includes: a memory bank module comprising a memory bank; and an operation module comprising a processing in memory (PIM) block, wherein the memory bank comprises: an array of memory cells arranged in a plurality of rows and a plurality of columns; a row buffer configured to store data of a row corresponding to a row address among the plurality of rows; and a selecting module configured to select first data and second data corresponding to a column address from among the data stored in the row buffer, wherein the first data is transmitted to the PIM block through a first data path connected between the selecting module and the PIM block, and the second data is transmitted to the PIM block through a second data path connected between the selecting module and the PIM block.

公开(公告)号：US20240419445A1

公开(公告)日：2024-12-19

申请号：US18814125

申请日：2024-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuhwan RO ,  Shinhaeng KANG ,  Seongil O ,  Seungwoo SEO

IPC: G06F9/30 ,  G06F9/50 ,  G06F12/06 ,  G06F13/16 ,  G06F15/78 ,  H03K19/173

Abstract: A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.

公开(公告)号：US20220107803A1

公开(公告)日：2022-04-07

申请号：US17314476

申请日：2021-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuhwan RO ,  Shinhaeng KANG ,  Seongil O ,  Seungwoo SEO

IPC: G06F9/30 ,  G06F9/50 ,  G06F13/16 ,  H03K19/173

Abstract: A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.

公开(公告)号：US20240184526A1

公开(公告)日：2024-06-06

申请号：US18329045

申请日：2023-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungwoo SEO ,  Sanghoon CHA

IPC: G06F7/544 ,  G06F7/502 ,  G06F9/30

CPC classification number: G06F7/5443 ,  G06F7/502 ,  G06F9/30145

Abstract: A memory device includes: a plurality of memory banks divided by a plurality of channels comprising a first channel and a second channel; and a channel-level processing element (PE) configured to generate an in-memory computation result by performing an operation using a first partial result generated based on data stored in a memory bank of the first channel among the plurality of memory banks and a second partial result generated based on data stored in a memory bank of the second channel among the plurality of memory banks.

公开(公告)号：US20240143230A1

公开(公告)日：2024-05-02

申请号：US18394392

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungwoo SEO ,  Seungwon LEE

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0673 ,  G06F15/7821

Abstract: A memory controller and a memory control method are disclosed. The memory controller includes a first buffer configured to receive a first memory request from a host and to store the first memory request, a request scheduler configured to determine an order in which the first memory request is transferred to a command generator, a request generator configured to generate one or more second memory requests based on a generation parameter of the first memory request, in response to an address of the first memory request corresponding to a processing in memory (PIM) memory, the command generator being configured to generate a first command corresponding to the first memory request and one or more second commands corresponding to the one or more second memory requests, and to store the generated first command and the one or more second commands in a second buffer, and a command scheduler configured to schedule the first command and the one or more second commands.

公开(公告)号：US20210398597A1

公开(公告)日：2021-12-23

申请号：US17462298

申请日：2021-08-31

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Seungwoo SEO ,  Byeongho KIM ,  Jaehyun PARK ,  Jungho AHN ,  Minbok WI ,  Sunjung LEE ,  Eojin LEE ,  Wonkyung JUNG ,  Jongwook CHUNG ,  Jaewan CHOI

IPC: G11C16/30 ,  G06N3/02 ,  G11C5/02 ,  G11C16/10

Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

公开(公告)号：US20210374536A1

公开(公告)日：2021-12-02

申请号：US17334204

申请日：2021-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Youyoung SONG ,  Seungwoo SEO ,  Jinwoo SHIN ,  Eunho YANG ,  Sungju HWANG

IPC: G06N3/08 ,  G06K9/62 ,  G06F16/901 ,  G06F16/903

Abstract: A method of training a retrosynthesis prediction model includes determining first attention information from first character string information of a product, based on first graph information of the product, encoding the first character string information, based on the determined first attention information, and determining second attention information from the first graph information and second graph information of a reactant. The method further includes decoding second character string information of the reactant, based on the determined second attention information, and training the retrosynthesis prediction model, based on the decoded second character string information.

公开(公告)号：US20220253247A1

公开(公告)日：2022-08-11

申请号：US17472990

申请日：2021-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo KIM ,  Seungwon LEE ,  Seungwoo SEO ,  Hosang YOON

IPC: G06F3/06

Abstract: A memory controller, a method of operating the memory controller, and an electronic device including the memory controller are disclosed. The method of operating a memory controller, comprising receiving, from a host core, a plurality of commands for a memory, identifying, from among the plurality of commands, processing in memory (PIM) commands to execute one or more operations in the memory, verifying ordering information from a data field in each of the PIM commands, and reordering the PIM commands based on the ordering information and transmitting the reordered PIM commands to the memory.

公开(公告)号：US20220253246A1

公开(公告)日：2022-08-11

申请号：US17408584

申请日：2021-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungwoo SEO ,  Seungwon LEE

IPC: G06F3/06

Abstract: A memory controller and a memory control method are disclosed. The memory controller includes a first buffer configured to receive a first memory request from a host and to store the first memory request, a request scheduler configured to determine an order in which the first memory request is transferred to a command generator, a request generator configured to generate one or more second memory requests based on a generation parameter of the first memory request, in response to an address of the first memory request corresponding to a processing in memory (PIM) memory, the command generator being configured to generate a first command corresponding to the first memory request and one or more second commands corresponding to the one or more second memory requests, and to store the generated first command and the one or more second commands in a second buffer, and a command scheduler configured to schedule the first command and the one or more second commands.

公开(公告)号：US20220156081A1

公开(公告)日：2022-05-19

申请号：US17323171

申请日：2021-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungwoo SEO ,  Hyunsoo KIM ,  Seungwon LEE

IPC: G06F9/38

Abstract: A processing-in-memory (PIM) and a method of outputting an instruction using a PIM. The PIM includes an internal processor, a memory, and a register configured to store instruction meta information. The memory is configured to store a lookup table generated by predicting a future instruction. The external processor is configured to retrieve an instruction corresponding to the instruction meta information from the lookup table in response to a PIM application programming interface (API) call instruction including the instruction meta information. The instruction corresponding to the instruction meta information is output based on a retrieval result.