公开(公告)号：US10825530B2

公开(公告)日：2020-11-03

申请号：US16226810

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Jin Song ,  Hyun-Wook Park ,  Bong-Soon Lim ,  Do-Bin Kim

IPC: G11C16/16 ,  G11C16/34 ,  G11C8/12 ,  G11C16/12 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56

Abstract: In a method of erasing data in a nonvolatile memory device including a memory block, it is determined whether a data erase characteristic for the memory block is degraded for each predetermined cycle. The memory block has a plurality of memory cells therein, the plurality of memory cells being stacked in a vertical direction relative to an underlying substrate. A data erase operation is performed by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.

公开(公告)号：US11688478B2

公开(公告)日：2023-06-27

申请号：US17694229

申请日：2022-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Jin Song ,  Hyun-Wook Park ,  Bong-Soon Lim ,  Do-Bin Kim

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/14 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: G11C16/349 ,  G11C16/0483 ,  G11C16/14 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.

公开(公告)号：US11289170B2

公开(公告)日：2022-03-29

申请号：US17021407

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Jin Song ,  Hyun-Wook Park ,  Bong-Soon Lim ,  Do-Bin Kim

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/14 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.