公开(公告)号：US11462464B2

公开(公告)日：2022-10-04

申请号：US17110542

申请日：2020-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-youn Kim ,  Seok-hyun Lee

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L25/065 ,  H01L21/48

Abstract: A fan-out semiconductor package including a redistribution line structure is provided. The fan-out semiconductor package includes a plurality of redistribution line insulating layers and a plurality of redistribution line patterns arranged on at least one of an upper surface and a lower surface of each of the plurality of redistribution line insulating layers; at least one semiconductor chip arranged on the redistribution line structure and occupying a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure; and a molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width that is greater than the horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulating layers have a cascade structure.

公开(公告)号：US11791286B2

公开(公告)日：2023-10-17

申请号：US17405487

申请日：2021-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-ji Min ,  Seok-hyun Lee

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/11 ,  H01L2224/02125 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/05556 ,  H01L2924/00012 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/11464 ,  H01L2924/00014 ,  H01L2224/11849 ,  H01L2924/00014

Abstract: Some example embodiments relate to a semiconductor device and a semiconductor package. The semiconductor package includes a substrate including a conductive layer, an insulating layer coating the substrate, the insulating layer including an opening exposing at least part of the conductive layer, and an under-bump metal layer electrically connected to the at least part of the conductive layer exposed through the opening, wherein the insulating layer includes at least one recess adjacent to the opening, and the under-bump metal layer fills the at least one recess. The semiconductor device and the semiconductor package may have improved drop test characteristics and impact resistance.

公开(公告)号：US20200219834A1

公开(公告)日：2020-07-09

申请号：US16819851

申请日：2020-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-youn KIM ,  Seok-hyun Lee ,  Youn-ji Min ,  Kyoung-lim Suk ,  Seok-won Lee

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/683 ,  H01L21/48 ,  H01L25/065 ,  H01L23/498

Abstract: Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.

公开(公告)号：US20200043853A1

公开(公告)日：2020-02-06

申请号：US16299340

申请日：2019-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-youn KIM ,  Seok-hyun Lee

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683

Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.

公开(公告)号：US20130292846A1

公开(公告)日：2013-11-07

申请号：US13768649

申请日：2013-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-hyun Lee ,  Sun-won Kang ,  Ho-geon Song

IPC: H01L23/538

CPC classification number: H01L23/538 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: Provided is a semiconductor package including a first semiconductor chip and a second semiconductor chip respectively disposed at a bottom and at a top so that active surfaces thereof face each other. Further includes is a first molding member for sealing the first semiconductor chip and exposing the active surface of the first semiconductor chip through a top surface, a first rewiring formed on the top surface of the first molding member and the active surface of the first semiconductor chip, a second rewiring formed on a bottom surface of the first molding member, a through-via for penetrating through the first molding member and electrically connecting the first and second rewirings, and a first connection member disposed between the first and second semiconductor chips. Also provided are various systems including same and various methods for making same.

Abstract translation: 提供了一种半导体封装，其包括分别设置在底部和顶部的第一半导体芯片和第二半导体芯片，使得其有效表面彼此面对。 还包括第一模制构件，用于密封第一半导体芯片并通过顶表面暴露第一半导体芯片的活性表面，第一重新布线形成在第一模制构件的顶表面上，第一半导体芯片的有源表面 ，形成在第一成型构件的底面上的第二重新布线，穿过第一成型构件并电连接第一和第二重新布置的通孔，以及设置在第一和第二半导体芯片之间的第一连接构件。 还提供了包括相同的各种系统和用于制造它们的各种方法。

公开(公告)号：US11710701B2

公开(公告)日：2023-07-25

申请号：US17743805

申请日：2022-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-youn Kim ,  Seok-hyun Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3675 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005

Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.

公开(公告)号：US12170249B2

公开(公告)日：2024-12-17

申请号：US18332494

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-youn Kim ,  Seok-hyun Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18

Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.

公开(公告)号：US11355440B2

公开(公告)日：2022-06-07

申请号：US17100171

申请日：2020-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-youn Kim ,  Seok-hyun Lee

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.

公开(公告)号：US11101231B2

公开(公告)日：2021-08-24

申请号：US16819851

申请日：2020-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-youn Kim ,  Seok-hyun Lee ,  Youn-ji Min ,  Kyoung-lim Suk ,  Seok-won Lee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L21/683 ,  H01L25/065 ,  H01L23/498

Abstract: Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.

公开(公告)号：US20200043840A1

公开(公告)日：2020-02-06

申请号：US16299307

申请日：2019-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-youn Kim ,  Seok-hyun Lee

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L23/538

Abstract: A fan-out semiconductor package including a redistribution line structure is provided. The fan-out semiconductor package includes a plurality of redistribution line insulating layers and a plurality of redistribution line patterns arranged on at least one of an upper surface and a lower surface of each of the plurality of redistribution line insulating layers; at least one semiconductor chip arranged on the redistribution line structure and occupying a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure; and a molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width that is greater than the horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulating layers have a cascade structure.