公开(公告)号：US09508657B2

公开(公告)日：2016-11-29

申请号：US14698353

申请日：2015-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Hyun Lee

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is provided. The semiconductor includes a semiconductor chip, a package substrate, and an electromagnetic interference (EMI) shielding layer. The package substrate, arranged under the semiconductor chip, is electrically connected to the semiconductor chip. The package substrate has a receiving groove. The EMI shielding layer is arranged in the receiving groove to shield EMI propagated from a lower surface of the semiconductor chip through the package substrate.

Abstract translation: 提供半导体器件。 半导体包括半导体芯片，封装基板和电磁干扰（EMI）屏蔽层。 布置在半导体芯片下方的封装基板电连接到半导体芯片。 封装基板具有接收槽。 EMI屏蔽层布置在接收槽中以屏蔽通过封装衬底从半导体芯片的下表面传播的EMI。

公开(公告)号：US09093439B2

公开(公告)日：2015-07-28

申请号：US13944224

申请日：2013-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hyun Lee ,  Jin-Woo Park

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00

Abstract: According to example embodiments, a semiconductor package includes: a lower molding element; a lower semiconductor chip in the lower molding element and having lower chip pads on an upper surface and at an areas close to first and second sides of the lower molding element; conductive pillars surrounding the lower semiconductor chip and passing through the lower molding element; an upper semiconductor chip on the upper surface of the lower molding element and lower semiconductor chip, the upper semiconductor chip having upper chip pads on a top surface and at areas close to third and the fourth sides of the upper semiconductor chip, and a connecting structure on the lower molding element and the upper semiconductor chip and electrically connecting each of the lower chip pads and upper chip pads to a corresponding conductive pillar. The upper semiconductor chip is substantially orthogonal to the lower semiconductor chip.

Abstract translation: 根据示例性实施例，半导体封装包括：下模制元件; 下部模制元件中的下部半导体芯片，并且在上表面和靠近下部模制元件的第一和第二侧的区域中具有下部芯片焊盘; 导电柱围绕下半导体芯片并通过下模制元件; 在下模塑元件的上表面上的上半导体芯片和下半导体芯片，上半导体芯片在顶表面上具有上芯片焊盘，并且在上半导体芯片的靠近第三和第四侧的区域处具有连接结构 在下模制元件和上半导体芯片上，并且将每个下芯片焊盘和上芯片焊盘电连接到相应的导电柱。 上半导体芯片基本上正交于下半导体芯片。

公开(公告)号：US20160064365A1

公开(公告)日：2016-03-03

申请号：US14626326

申请日：2015-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-GWON JANG ,  Seok-Hyun Lee ,  Ae-Nee Jang

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a package substrate having a lower substrate and an upper substrate disposed on the lower substrate, the package substrate having a first cavity, a first semiconductor chip disposed in the first cavity, and a chip stack disposed to partially cover the first cavity on the upper substrate.

Abstract translation: 半导体封装包括具有下基板和设置在下基板上的上基板的封装基板，封装基板具有第一空腔，设置在第一空腔中的第一半导体芯片和设置成部分地覆盖第一空腔的芯片堆叠 在上基板上。

公开(公告)号：US08927340B2

公开(公告)日：2015-01-06

申请号：US13772427

申请日：2013-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Woo Park ,  Seok-Hyun Lee ,  Ho-Geon Song

IPC: H01L21/44 ,  H01L21/50 ,  H01L23/00

CPC classification number: H01L21/50 ,  H01L21/568 ,  H01L24/19 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Provided are a double-sided adhesive tape, semiconductor packages, and methods of fabricating the packages. A method of fabricating semiconductor packages includes providing a double-sided adhesive tape on a top surface of a carrier, the double-sided adhesive tape including a first adhesive layer and a second adhesive layer stacked on the first adhesive layer, the first adhesive layer of the double-sided adhesive tape being in contact with the top surface of the carrier, adhering active surfaces of a plurality of semiconductor chips onto the second adhesive layer of the double-sided adhesive tape, separating the first adhesive layer from the second adhesive layer such that the second adhesive layer remains on the active surfaces of the semiconductor chips, patterning the second adhesive layer to form first openings that selectively expose the active surfaces of the semiconductor chips, and forming first conductive components on the second adhesive layer to fill the first openings.

Abstract translation: 提供双面胶带，半导体封装以及制造封装的方法。 制造半导体封装的方法包括在载体的顶表面上提供双面胶带，所述双面胶带包括第一粘合剂层和层叠在第一粘合剂层上的第二粘合剂层，第一粘合剂层 所述双面胶带与所述载体的顶表面接触，将多个半导体芯片的活性表面粘合到所述双面胶带的第二粘合剂层上，从而将所述第一粘合剂层与所​​述第二粘合层分离， 第二粘合剂层保留在半导体芯片的有效表面上，图案化第二粘合剂层以形成选择性地暴露半导体芯片的有效表面的第一开口，以及在第二粘合剂层上形成第一导电部件以填充第一开口 。